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authorJim Lawson2016-09-15 09:54:20 -0700
committerJim Lawson2016-09-15 09:54:20 -0700
commit36f77e86bbf1f471b158f36deae6a14f1d623075 (patch)
tree9b0060b03aa9c048645b0f624598adc93088d40e /src/main/scala/chisel3/package.scala
parent19f5b7c6841bda318288990e643eb02fa22a49e2 (diff)
parent2ff229dac5f915e7f583cbf9cc8118674a4e52a5 (diff)
Merge branch 'master' into gsdt
Diffstat (limited to 'src/main/scala/chisel3/package.scala')
-rw-r--r--src/main/scala/chisel3/package.scala53
1 files changed, 53 insertions, 0 deletions
diff --git a/src/main/scala/chisel3/package.scala b/src/main/scala/chisel3/package.scala
index 7911cb04..8f01779f 100644
--- a/src/main/scala/chisel3/package.scala
+++ b/src/main/scala/chisel3/package.scala
@@ -59,6 +59,58 @@ package object chisel3 { // scalastyle:ignore package.object.name
val when = chisel3.core.when
type WhenContext = chisel3.core.WhenContext
+ type Printable = chisel3.core.Printable
+ val Printable = chisel3.core.Printable
+ type Printables = chisel3.core.Printables
+ val Printables = chisel3.core.Printables
+ type PString = chisel3.core.PString
+ val PString = chisel3.core.PString
+ type FirrtlFormat = chisel3.core.FirrtlFormat
+ val FirrtlFormat = chisel3.core.FirrtlFormat
+ type Decimal = chisel3.core.Decimal
+ val Decimal = chisel3.core.Decimal
+ type Hexadecimal = chisel3.core.Hexadecimal
+ val Hexadecimal = chisel3.core.Hexadecimal
+ type Binary = chisel3.core.Binary
+ val Binary = chisel3.core.Binary
+ type Character = chisel3.core.Character
+ val Character = chisel3.core.Character
+ type Name = chisel3.core.Name
+ val Name = chisel3.core.Name
+ type FullName = chisel3.core.FullName
+ val FullName = chisel3.core.FullName
+ val Percent = chisel3.core.Percent
+
+ /** Implicit for custom Printable string interpolator */
+ implicit class PrintableHelper(val sc: StringContext) extends AnyVal {
+ /** Custom string interpolator for generating Printables: p"..."
+ * Will call .toString on any non-Printable arguments (mimicking s"...")
+ */
+ def p(args: Any*): Printable = {
+ sc.checkLengths(args) // Enforce sc.parts.size == pargs.size + 1
+ val pargs: Seq[Option[Printable]] = args map {
+ case p: Printable => Some(p)
+ case d: Data => Some(d.toPrintable)
+ case any => for {
+ v <- Option(any) // Handle null inputs
+ str = v.toString
+ if !str.isEmpty // Handle empty Strings
+ } yield PString(str)
+ }
+ val parts = sc.parts map StringContext.treatEscapes
+ // Zip sc.parts and pargs together ito flat Seq
+ // eg. Seq(sc.parts(0), pargs(0), sc.parts(1), pargs(1), ...)
+ val seq = for { // append None because sc.parts.size == pargs.size + 1
+ (literal, arg) <- parts zip (pargs :+ None)
+ optPable <- Seq(Some(PString(literal)), arg)
+ pable <- optPable // Remove Option[_]
+ } yield pable
+ Printables(seq)
+ }
+ }
+
+ implicit def string2Printable(str: String): Printable = PString(str)
+
/**
* These implicit classes allow one to convert scala.Int|scala.BigInt to
* Chisel.UInt|Chisel.SInt by calling .asUInt|.asSInt on them, respectively.
@@ -144,4 +196,5 @@ package object chisel3 { // scalastyle:ignore package.object.name
a.allElements
}
def getModulePorts(m: Module): Seq[Port] = m.getPorts
+ def getFirrtlDirection(d: Data): Direction = chisel3.core.Data.getFirrtlDirection(d)
}