Merge branch 'sdtwigg_rebase_renamechisel3' into sdtwigg_wrap_renamechisel3

1 files changed, 19 insertions, 0 deletions

diff --git a/src/main/scala/chisel3/compatibility/Main.scala b/src/main/scala/chisel3/compatibility/Main.scala
new file mode 100644
index 00000000..a41599a3
--- /dev/null
+++ b/src/main/scala/chisel3/compatibility/Main.scala
@@ -0,0 +1,19 @@
+// See LICENSE for license details.
+
+package chisel3.compatibility
+
+import java.io.File
+
+import chisel3._
+
+@deprecated("chiselMain doesn't exist in Chisel3", "3.0") object chiselMain {
+  def apply[T <: Module](args: Array[String], gen: () => T): Unit =
+    Predef.assert(false, "No more chiselMain in Chisel3")
+
+  def run[T <: Module] (args: Array[String], gen: () => T): Unit = {
+    val circuit = Driver.elaborate(gen)
+    Driver.parseArgs(args)
+    val output_file = new File(Driver.targetDir + "/" + circuit.name + ".fir")
+    Driver.dumpFirrtl(circuit, Option(output_file))
+  }
+}