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authorJim Lawson2020-01-21 15:15:10 -0800
committerGitHub2020-01-21 15:15:10 -0800
commitd70543a2bd74c2bde5abb114b946750b46a39d25 (patch)
treea2177d93b2d1973cf42673d552114c9ee2269179 /src/main/scala/chisel3/aop
parentc4aa70f64ad5ecd8a5557ad0e4777f245768d865 (diff)
parentc7715c160a0dd07765e736b813c8b6b26b27de28 (diff)
Merge branch 'master' into add-asbool-to-clock
Diffstat (limited to 'src/main/scala/chisel3/aop')
-rw-r--r--src/main/scala/chisel3/aop/Select.scala7
1 files changed, 5 insertions, 2 deletions
diff --git a/src/main/scala/chisel3/aop/Select.scala b/src/main/scala/chisel3/aop/Select.scala
index 612cdcc7..390f82a5 100644
--- a/src/main/scala/chisel3/aop/Select.scala
+++ b/src/main/scala/chisel3/aop/Select.scala
@@ -80,8 +80,11 @@ object Select {
*/
def instances(module: BaseModule): Seq[BaseModule] = {
check(module)
- module._component.get.asInstanceOf[DefModule].commands.collect {
- case i: DefInstance => i.id
+ module._component.get match {
+ case d: DefModule => d.commands.collect {
+ case i: DefInstance => i.id
+ }
+ case other => Nil
}
}