cleanup

3 files changed, 165 insertions, 165 deletions

diff --git a/src/main/scala/chisel3/aop/injecting/InjectStatement.scala b/src/main/scala/chisel3/aop/injecting/InjectStatement.scala
index dbe1fd7b..be12cf32 100644
--- a/src/main/scala/chisel3/aop/injecting/InjectStatement.scala
+++ b/src/main/scala/chisel3/aop/injecting/InjectStatement.scala
@@ -1,26 +1,26 @@
-// SPDX-License-Identifier: Apache-2.0
+// // SPDX-License-Identifier: Apache-2.0
 
-package chisel3.aop.injecting
+// package chisel3.aop.injecting
 
-import chisel3.stage.phases.AspectPhase
-import firrtl.annotations.{Annotation, ModuleTarget, NoTargetAnnotation, SingleTargetAnnotation}
+// import chisel3.stage.phases.AspectPhase
+// import firrtl.annotations.{Annotation, ModuleTarget, NoTargetAnnotation, SingleTargetAnnotation}
 
-/** Contains all information needed to inject statements into a module
-  *
-  * Generated when a [[InjectingAspect]] is consumed by a [[AspectPhase]]
-  * Consumed by [[InjectingTransform]]
-  *
-  * @param module Module to inject code into at the end of the module
-  * @param s Statements to inject
-  * @param modules Additional modules that may be instantiated by s
-  * @param annotations Additional annotations that should be passed down compiler
-  */
-case class InjectStatement(
-  module:      ModuleTarget,
-  s:           firrtl.ir.Statement,
-  modules:     Seq[firrtl.ir.DefModule],
-  annotations: Seq[Annotation])
-    extends SingleTargetAnnotation[ModuleTarget] {
-  val target: ModuleTarget = module
-  override def duplicate(n: ModuleTarget): Annotation = this.copy(module = n)
-}
+// /** Contains all information needed to inject statements into a module
+//   *
+//   * Generated when a [[InjectingAspect]] is consumed by a [[AspectPhase]]
+//   * Consumed by [[InjectingTransform]]
+//   *
+//   * @param module Module to inject code into at the end of the module
+//   * @param s Statements to inject
+//   * @param modules Additional modules that may be instantiated by s
+//   * @param annotations Additional annotations that should be passed down compiler
+//   */
+// case class InjectStatement(
+//   module:      ModuleTarget,
+//   s:           firrtl.ir.Statement,
+//   modules:     Seq[firrtl.ir.DefModule],
+//   annotations: Seq[Annotation])
+//     extends SingleTargetAnnotation[ModuleTarget] {
+//   val target: ModuleTarget = module
+//   override def duplicate(n: ModuleTarget): Annotation = this.copy(module = n)
+// }
diff --git a/src/main/scala/chisel3/aop/injecting/InjectingAspect.scala b/src/main/scala/chisel3/aop/injecting/InjectingAspect.scala
index ecce19e1..8682785b 100644
--- a/src/main/scala/chisel3/aop/injecting/InjectingAspect.scala
+++ b/src/main/scala/chisel3/aop/injecting/InjectingAspect.scala
@@ -1,108 +1,108 @@
-// SPDX-License-Identifier: Apache-2.0
+// // SPDX-License-Identifier: Apache-2.0
 
-package chisel3.aop.injecting
+// package chisel3.aop.injecting
 
-import chisel3.{withClockAndReset, Module, ModuleAspect, RawModule}
-import chisel3.aop._
-import chisel3.internal.{Builder, DynamicContext}
-import chisel3.internal.firrtl.DefModule
-import chisel3.stage.{ChiselOptions, DesignAnnotation}
-import firrtl.annotations.ModuleTarget
-import firrtl.stage.RunFirrtlTransformAnnotation
-import firrtl.options.Viewer.view
-import firrtl.{ir, _}
+// import chisel3.{withClockAndReset, Module, ModuleAspect, RawModule}
+// import chisel3.aop._
+// import chisel3.internal.{Builder, DynamicContext}
+// import chisel3.internal.firrtl.DefModule
+// import chisel3.stage.{ChiselOptions, DesignAnnotation}
+// import firrtl.annotations.ModuleTarget
+// import firrtl.stage.RunFirrtlTransformAnnotation
+// import firrtl.options.Viewer.view
+// import firrtl.{ir, _}
 
-import scala.collection.mutable
+// import scala.collection.mutable
 
-/** Aspect to inject Chisel code into a module of type M
-  *
-  * @param selectRoots Given top-level module, pick the instances of a module to apply the aspect (root module)
-  * @param injection Function to generate Chisel hardware that will be injected to the end of module m
-  *                  Signals in m can be referenced and assigned to as if inside m (yes, it is a bit magical)
-  * @tparam T Type of top-level module
-  * @tparam M Type of root module (join point)
-  */
-case class InjectingAspect[T <: RawModule, M <: RawModule](
-  selectRoots: T => Iterable[M],
-  injection:   M => Unit)
-    extends InjectorAspect[T, M](
-      selectRoots,
-      injection
-    )
+// /** Aspect to inject Chisel code into a module of type M
+//   *
+//   * @param selectRoots Given top-level module, pick the instances of a module to apply the aspect (root module)
+//   * @param injection Function to generate Chisel hardware that will be injected to the end of module m
+//   *                  Signals in m can be referenced and assigned to as if inside m (yes, it is a bit magical)
+//   * @tparam T Type of top-level module
+//   * @tparam M Type of root module (join point)
+//   */
+// case class InjectingAspect[T <: RawModule, M <: RawModule](
+//   selectRoots: T => Iterable[M],
+//   injection:   M => Unit)
+//     extends InjectorAspect[T, M](
+//       selectRoots,
+//       injection
+//     )
 
-/** Extend to inject Chisel code into a module of type M
-  *
-  * @param selectRoots Given top-level module, pick the instances of a module to apply the aspect (root module)
-  * @param injection Function to generate Chisel hardware that will be injected to the end of module m
-  *                  Signals in m can be referenced and assigned to as if inside m (yes, it is a bit magical)
-  * @tparam T Type of top-level module
-  * @tparam M Type of root module (join point)
-  */
-abstract class InjectorAspect[T <: RawModule, M <: RawModule](
-  selectRoots: T => Iterable[M],
-  injection:   M => Unit)
-    extends Aspect[T] {
-  final def toAnnotation(top: T): AnnotationSeq = {
-    val moduleNames =
-      Select.allDefinitionsOf[chisel3.experimental.BaseModule](top.toDefinition).map { i => i.toTarget.module }.toSeq
-    toAnnotation(selectRoots(top), top.name, moduleNames)
-  }
+// /** Extend to inject Chisel code into a module of type M
+//   *
+//   * @param selectRoots Given top-level module, pick the instances of a module to apply the aspect (root module)
+//   * @param injection Function to generate Chisel hardware that will be injected to the end of module m
+//   *                  Signals in m can be referenced and assigned to as if inside m (yes, it is a bit magical)
+//   * @tparam T Type of top-level module
+//   * @tparam M Type of root module (join point)
+//   */
+// abstract class InjectorAspect[T <: RawModule, M <: RawModule](
+//   selectRoots: T => Iterable[M],
+//   injection:   M => Unit)
+//     extends Aspect[T] {
+//   final def toAnnotation(top: T): AnnotationSeq = {
+//     val moduleNames =
+//       Select.allDefinitionsOf[chisel3.experimental.BaseModule](top.toDefinition).map { i => i.toTarget.module }.toSeq
+//     toAnnotation(selectRoots(top), top.name, moduleNames)
+//   }
 
-  /** Returns annotations which contain all injection logic
-    *
-    * @param modules The modules to inject into
-    * @param circuit Top level circuit
-    * @param moduleNames The names of all existing modules in the original circuit, to avoid name collisions
-    * @return
-    */
-  final def toAnnotation(modules: Iterable[M], circuit: String, moduleNames: Seq[String]): AnnotationSeq = {
-    RunFirrtlTransformAnnotation(new InjectingTransform) +: modules.map { module =>
-      val chiselOptions = view[ChiselOptions](annotationsInAspect)
-      val dynamicContext =
-        new DynamicContext(
-          annotationsInAspect,
-          chiselOptions.throwOnFirstError,
-          chiselOptions.warnReflectiveNaming,
-          chiselOptions.warningsAsErrors
-        )
-      // Add existing module names into the namespace. If injection logic instantiates new modules
-      //  which would share the same name, they will get uniquified accordingly
-      moduleNames.foreach { n =>
-        dynamicContext.globalNamespace.name(n)
-      }
+//   /** Returns annotations which contain all injection logic
+//     *
+//     * @param modules The modules to inject into
+//     * @param circuit Top level circuit
+//     * @param moduleNames The names of all existing modules in the original circuit, to avoid name collisions
+//     * @return
+//     */
+//   final def toAnnotation(modules: Iterable[M], circuit: String, moduleNames: Seq[String]): AnnotationSeq = {
+//     RunFirrtlTransformAnnotation(new InjectingTransform) +: modules.map { module =>
+//       val chiselOptions = view[ChiselOptions](annotationsInAspect)
+//       val dynamicContext =
+//         new DynamicContext(
+//           annotationsInAspect,
+//           chiselOptions.throwOnFirstError,
+//           chiselOptions.warnReflectiveNaming,
+//           chiselOptions.warningsAsErrors
+//         )
+//       // Add existing module names into the namespace. If injection logic instantiates new modules
+//       //  which would share the same name, they will get uniquified accordingly
+//       moduleNames.foreach { n =>
+//         dynamicContext.globalNamespace.name(n)
+//       }
 
-      val (chiselIR, _) = Builder.build(
-        Module(new ModuleAspect(module) {
-          module match {
-            case x: Module    => withClockAndReset(x.clock, x.reset) { injection(module) }
-            case x: RawModule => injection(module)
-          }
-        }),
-        dynamicContext
-      )
+//       val (chiselIR, _) = Builder.build(
+//         Module(new ModuleAspect(module) {
+//           module match {
+//             case x: Module    => withClockAndReset(x.clock, x.reset) { injection(module) }
+//             case x: RawModule => injection(module)
+//           }
+//         }),
+//         dynamicContext
+//       )
 
-      val comps = chiselIR.components.map {
-        case x: DefModule if x.name == module.name => x.copy(id = module)
-        case other => other
-      }
+//       val comps = chiselIR.components.map {
+//         case x: DefModule if x.name == module.name => x.copy(id = module)
+//         case other => other
+//       }
 
-      val annotations = chiselIR.annotations.map(_.toFirrtl).filterNot { a => a.isInstanceOf[DesignAnnotation[_]] }
+//       val annotations = chiselIR.annotations.map(_.toFirrtl).filterNot { a => a.isInstanceOf[DesignAnnotation[_]] }
 
-      /** Statements to be injected via aspect. */
-      val stmts = mutable.ArrayBuffer[ir.Statement]()
+//       /** Statements to be injected via aspect. */
+//       val stmts = mutable.ArrayBuffer[ir.Statement]()
 
-      /** Modules to be injected via aspect. */
-      val modules = Aspect.getFirrtl(chiselIR.copy(components = comps)).modules.flatMap {
-        // for "container" modules, inject their statements
-        case m: firrtl.ir.Module if m.name == module.name =>
-          stmts += m.body
-          Nil
-        // for modules to be injected
-        case other: firrtl.ir.DefModule =>
-          Seq(other)
-      }
+//       /** Modules to be injected via aspect. */
+//       val modules = Aspect.getFirrtl(chiselIR.copy(components = comps)).modules.flatMap {
+//         // for "container" modules, inject their statements
+//         case m: firrtl.ir.Module if m.name == module.name =>
+//           stmts += m.body
+//           Nil
+//         // for modules to be injected
+//         case other: firrtl.ir.DefModule =>
+//           Seq(other)
+//       }
 
-      InjectStatement(ModuleTarget(circuit, module.name), ir.Block(stmts.toSeq), modules, annotations)
-    }.toSeq
-  }
-}
+//       InjectStatement(ModuleTarget(circuit, module.name), ir.Block(stmts.toSeq), modules, annotations)
+//     }.toSeq
+//   }
+// }
diff --git a/src/main/scala/chisel3/aop/injecting/InjectingTransform.scala b/src/main/scala/chisel3/aop/injecting/InjectingTransform.scala
index 8a0b6ecb..a7d47243 100644
--- a/src/main/scala/chisel3/aop/injecting/InjectingTransform.scala
+++ b/src/main/scala/chisel3/aop/injecting/InjectingTransform.scala
@@ -1,46 +1,46 @@
-// SPDX-License-Identifier: Apache-2.0
-
-package chisel3.aop.injecting
-
-import firrtl.{ir, ChirrtlForm, CircuitForm, CircuitState, Transform}
-
-import scala.collection.mutable
-
-/** Appends statements contained in [[InjectStatement]] annotations to the end of their corresponding modules
-  *
-  * Implemented with Chisel Aspects and the [[chisel3.aop.injecting]] library
-  */
-class InjectingTransform extends Transform {
-  override def inputForm:  CircuitForm = ChirrtlForm
-  override def outputForm: CircuitForm = ChirrtlForm
-
-  override def execute(state: CircuitState): CircuitState = {
-
-    val addStmtMap = mutable.HashMap[String, Seq[ir.Statement]]()
-    val addModules = mutable.ArrayBuffer[ir.DefModule]()
-
-    // Populate addStmtMap and addModules, return annotations in InjectStatements, and omit InjectStatement annotation
-    val newAnnotations = state.annotations.flatMap {
-      case InjectStatement(mt, s, addedModules, annotations) =>
-        addModules ++= addedModules
-        addStmtMap(mt.module) = s +: addStmtMap.getOrElse(mt.module, Nil)
-        annotations
-      case other => Seq(other)
-    }
-
-    // Append all statements to end of corresponding modules
-    val newModules = state.circuit.modules.map { m: ir.DefModule =>
-      m match {
-        case m: ir.Module if addStmtMap.contains(m.name) =>
-          m.copy(body = ir.Block(m.body +: addStmtMap(m.name)))
-        case m: _root_.firrtl.ir.ExtModule if addStmtMap.contains(m.name) =>
-          ir.Module(m.info, m.name, m.ports, ir.Block(addStmtMap(m.name)))
-        case other: ir.DefModule => other
-      }
-    }
-
-    // Return updated circuit and annotations
-    val newCircuit = state.circuit.copy(modules = newModules ++ addModules)
-    state.copy(annotations = newAnnotations, circuit = newCircuit)
-  }
-}
+// // SPDX-License-Identifier: Apache-2.0
+
+// package chisel3.aop.injecting
+
+// import firrtl.{ir, ChirrtlForm, CircuitForm, CircuitState, Transform}
+
+// import scala.collection.mutable
+
+// /** Appends statements contained in [[InjectStatement]] annotations to the end of their corresponding modules
+//   *
+//   * Implemented with Chisel Aspects and the [[chisel3.aop.injecting]] library
+//   */
+// class InjectingTransform extends Transform {
+//   override def inputForm:  CircuitForm = ChirrtlForm
+//   override def outputForm: CircuitForm = ChirrtlForm
+
+//   override def execute(state: CircuitState): CircuitState = {
+
+//     val addStmtMap = mutable.HashMap[String, Seq[ir.Statement]]()
+//     val addModules = mutable.ArrayBuffer[ir.DefModule]()
+
+//     // Populate addStmtMap and addModules, return annotations in InjectStatements, and omit InjectStatement annotation
+//     val newAnnotations = state.annotations.flatMap {
+//       case InjectStatement(mt, s, addedModules, annotations) =>
+//         addModules ++= addedModules
+//         addStmtMap(mt.module) = s +: addStmtMap.getOrElse(mt.module, Nil)
+//         annotations
+//       case other => Seq(other)
+//     }
+
+//     // Append all statements to end of corresponding modules
+//     val newModules = state.circuit.modules.map { m: ir.DefModule =>
+//       m match {
+//         case m: ir.Module if addStmtMap.contains(m.name) =>
+//           m.copy(body = ir.Block(m.body +: addStmtMap(m.name)))
+//         case m: _root_.firrtl.ir.ExtModule if addStmtMap.contains(m.name) =>
+//           ir.Module(m.info, m.name, m.ports, ir.Block(addStmtMap(m.name)))
+//         case other: ir.DefModule => other
+//       }
+//     }
+
+//     // Return updated circuit and annotations
+//     val newCircuit = state.circuit.copy(modules = newModules ++ addModules)
+//     state.copy(annotations = newAnnotations, circuit = newCircuit)
+//   }
+// }