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| author | Jim Lawson | 2016-10-06 08:57:10 -0700 |
|---|---|---|
| committer | Jim Lawson | 2016-10-06 08:57:10 -0700 |
| commit | 82625071405672eb4a19363d6f73f359ac28a7f5 (patch) | |
| tree | dee5beff0e7333fa86c1cdcdb79c0d111114b8c9 /src/main/scala/Chisel/util/LFSR.scala | |
| parent | b7c6e0d1a2098b545938a5a8dfce2b1d9294532f (diff) | |
| parent | 7de30c2b893a3f24d43f2e131557430eb64f6bc8 (diff) | |
Merge branch 'master' into tobits-deprecation
Diffstat (limited to 'src/main/scala/Chisel/util/LFSR.scala')
| -rw-r--r-- | src/main/scala/Chisel/util/LFSR.scala | 22 |
1 files changed, 0 insertions, 22 deletions
diff --git a/src/main/scala/Chisel/util/LFSR.scala b/src/main/scala/Chisel/util/LFSR.scala deleted file mode 100644 index 839b1d1f..00000000 --- a/src/main/scala/Chisel/util/LFSR.scala +++ /dev/null @@ -1,22 +0,0 @@ -// See LICENSE for license details. - -/** LFSRs in all shapes and sizes. - */ - -package Chisel - -// scalastyle:off magic.number -/** linear feedback shift register - */ -object LFSR16 -{ - def apply(increment: Bool = Bool(true)): UInt = - { - val width = 16 - val lfsr = Reg(init=UInt(1, width)) - when (increment) { lfsr := Cat(lfsr(0)^lfsr(2)^lfsr(3)^lfsr(5), lfsr(width-1,1)) } - lfsr - } -} -// scalastyle:on magic.number - |