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authorPalmer Dabbelt2015-11-02 13:29:15 -0800
committerPalmer Dabbelt2015-11-02 13:29:15 -0800
commit3ccc3d5728e17fae6fe41a396479a9114d3af7d5 (patch)
treeb4bcdd586123b571a2f53b6726e501003dd46119 /src/main/scala/Chisel/util/LFSR.scala
parent178f5c564e9ab0594656185e2e0a5bcc029d5743 (diff)
parent6c34949c45cf7ddfdabafb749de2cb9e439b381e (diff)
Merge pull request #37 from ucb-bar/utilsplit
Break out Utils.scala into smaller portions
Diffstat (limited to 'src/main/scala/Chisel/util/LFSR.scala')
-rw-r--r--src/main/scala/Chisel/util/LFSR.scala22
1 files changed, 22 insertions, 0 deletions
diff --git a/src/main/scala/Chisel/util/LFSR.scala b/src/main/scala/Chisel/util/LFSR.scala
new file mode 100644
index 00000000..839b1d1f
--- /dev/null
+++ b/src/main/scala/Chisel/util/LFSR.scala
@@ -0,0 +1,22 @@
+// See LICENSE for license details.
+
+/** LFSRs in all shapes and sizes.
+ */
+
+package Chisel
+
+// scalastyle:off magic.number
+/** linear feedback shift register
+ */
+object LFSR16
+{
+ def apply(increment: Bool = Bool(true)): UInt =
+ {
+ val width = 16
+ val lfsr = Reg(init=UInt(1, width))
+ when (increment) { lfsr := Cat(lfsr(0)^lfsr(2)^lfsr(3)^lfsr(5), lfsr(width-1,1)) }
+ lfsr
+ }
+}
+// scalastyle:on magic.number
+