diff options
| author | Andrew Waterman | 2016-05-02 20:11:58 -0700 |
|---|---|---|
| committer | Andrew Waterman | 2016-05-04 01:48:35 -0700 |
| commit | cd951e193ed6a52c5146583a826e3cae5374d07b (patch) | |
| tree | 754e152d44d44e0bdd24ddede4a554d0d11eb32d /src/main/scala/Chisel/util/Cat.scala | |
| parent | bb912f52606d6c11c00dd035af1a4e0033dd091c (diff) | |
Remove dependences from Chisel core on Chisel utils
Partially resolves #164
Diffstat (limited to 'src/main/scala/Chisel/util/Cat.scala')
| -rw-r--r-- | src/main/scala/Chisel/util/Cat.scala | 10 |
1 files changed, 1 insertions, 9 deletions
diff --git a/src/main/scala/Chisel/util/Cat.scala b/src/main/scala/Chisel/util/Cat.scala index 088a208e..dd706e62 100644 --- a/src/main/scala/Chisel/util/Cat.scala +++ b/src/main/scala/Chisel/util/Cat.scala @@ -14,13 +14,5 @@ object Cat { * @param r any number of other Data elements to be combined in order * @return A UInt which is all of the bits combined together */ - def apply[T <: Bits](r: Seq[T]): UInt = { - if (r.tail.isEmpty) { - r.head.asUInt - } else { - val left = apply(r.slice(0, r.length/2)) - val right = apply(r.slice(r.length/2, r.length)) - left ## right - } - } + def apply[T <: Bits](r: Seq[T]): UInt = SeqUtils.asUInt(r.reverse) } |
