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| author | Jim Lawson | 2016-06-03 12:38:28 -0700 |
|---|---|---|
| committer | Jim Lawson | 2016-06-03 12:38:28 -0700 |
| commit | 9dd286b8613beba58e053ed00d15877d3a4b02c9 (patch) | |
| tree | 6ae9268d8e7e6532e5b8a0f3ad51d6c345623376 /src/main/scala/Chisel/testers/TesterDriver.scala | |
| parent | 70271cd8c3811cb518e81d1d5eb3ed20cb1e2063 (diff) | |
| parent | fd53af8642237998e23456a3fd1648ac84607db0 (diff) | |
Merge branch 'master' into front_end_dependency
Diffstat (limited to 'src/main/scala/Chisel/testers/TesterDriver.scala')
| -rw-r--r-- | src/main/scala/Chisel/testers/TesterDriver.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/Chisel/testers/TesterDriver.scala b/src/main/scala/Chisel/testers/TesterDriver.scala index c0cdfb3f..a56bb8b7 100644 --- a/src/main/scala/Chisel/testers/TesterDriver.scala +++ b/src/main/scala/Chisel/testers/TesterDriver.scala @@ -47,7 +47,7 @@ object TesterDriver extends BackendCompilationUtilities { // Use sys.Process to invoke a bunch of backend stuff, then run the resulting exe if ((firrtlToVerilog(target, path) #&& - verilogToCpp(target, path, additionalVFiles, cppHarness) #&& + verilogToCpp(target, target, path, additionalVFiles, cppHarness) #&& cppToExe(target, path)).! == 0) { executeExpectingSuccess(target, path) } else { |