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| author | Henry Cook | 2015-11-04 09:21:07 -0800 |
|---|---|---|
| committer | Henry Cook | 2015-11-04 09:21:07 -0800 |
| commit | a3c9680d1e2b84693759747a4779341ba80c4a50 (patch) | |
| tree | e97ab1d8394b0463ec7f600fce7ba278bd68d93a /src/main/scala/Chisel/ir | |
| parent | 23d15d166d2ed32f8bd9a153a806c09982659011 (diff) | |
Remove Parameters library and refactor Driver.
In addition to removing all the extraneous Driver invocations that created various top-level Parameters instances,
this commit also lays the groundwork for stanza-firrtl/verilator based testing of Modules that extend BasicTester.
The execution-based tests have been updated accordingly. They will only succeed if firrtl and verilator binaries have been installed.
Further work is needed on individual tests to use assertions instead of .io.error.
Diffstat (limited to 'src/main/scala/Chisel/ir')
| -rw-r--r-- | src/main/scala/Chisel/ir/IR.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/Chisel/ir/IR.scala b/src/main/scala/Chisel/ir/IR.scala index e25d3f56..106ad20c 100644 --- a/src/main/scala/Chisel/ir/IR.scala +++ b/src/main/scala/Chisel/ir/IR.scala @@ -152,6 +152,6 @@ case class ConnectInit(loc: Node, exp: Arg) extends Command case class Component(id: Module, name: String, ports: Seq[Port], commands: Seq[Command]) extends Arg case class Port(id: Data, dir: Direction) -case class Circuit(name: String, components: Seq[Component], refMap: RefMap, parameterDump: ParameterDump) { +case class Circuit(name: String, components: Seq[Component], refMap: RefMap) { def emit: String = new Emitter(this).toString } |
