diff options
| author | Andrew Waterman | 2016-01-28 12:05:03 -0800 |
|---|---|---|
| committer | Andrew Waterman | 2016-01-28 12:05:03 -0800 |
| commit | 41674d5e130f64d7489fdb8583b8f4ad88b64aeb (patch) | |
| tree | 9df546ee0291e77aebbae0b752bbde961c752c63 /src/main/scala/Chisel/internal/firrtl/IR.scala | |
| parent | bce4a96934fe8575b71769f2e52a2b75a068d34d (diff) | |
Use FIRRTL is invalid construct
Diffstat (limited to 'src/main/scala/Chisel/internal/firrtl/IR.scala')
| -rw-r--r-- | src/main/scala/Chisel/internal/firrtl/IR.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/Chisel/internal/firrtl/IR.scala b/src/main/scala/Chisel/internal/firrtl/IR.scala index 3e923366..7bb273c0 100644 --- a/src/main/scala/Chisel/internal/firrtl/IR.scala +++ b/src/main/scala/Chisel/internal/firrtl/IR.scala @@ -147,6 +147,7 @@ abstract class Definition extends Command { def name: String = id.getRef.name } case class DefPrim[T <: Data](id: T, op: PrimOp, args: Arg*) extends Definition +case class DefInvalid(arg: Arg) extends Command case class DefWire(id: Data) extends Definition case class DefReg(id: Data, clock: Arg) extends Definition case class DefRegInit(id: Data, clock: Arg, reset: Arg, init: Arg) extends Definition @@ -154,7 +155,6 @@ case class DefMemory(id: HasId, t: Data, size: Int) extends Definition case class DefSeqMemory(id: HasId, t: Data, size: Int) extends Definition case class DefMemPort[T <: Data](id: T, source: Node, dir: MemPortDirection, index: Arg, clock: Arg) extends Definition case class DefInstance(id: Module, ports: Seq[Port]) extends Definition -case class DefPoison[T <: Data](id: T) extends Definition case class WhenBegin(pred: Arg) extends Command case class WhenEnd() extends Command case class Connect(loc: Node, exp: Arg) extends Command |