diff options
| author | Andrew Waterman | 2016-01-28 12:25:17 -0800 |
|---|---|---|
| committer | Andrew Waterman | 2016-01-28 12:25:17 -0800 |
| commit | a6cdcecb7920b661de09948609674b89f21b985f (patch) | |
| tree | 11fb062f11c784287a0c63f933a0e3d9f863b702 /src/main/scala/Chisel/internal/firrtl/IR.scala | |
| parent | ccc88bbd9d462f04fe1dd39327349aeea8de9d3c (diff) | |
| parent | f9977fb4e5508032c3e17d201f747e71a32b9311 (diff) | |
Merge branch 'master' into modrefactor
Diffstat (limited to 'src/main/scala/Chisel/internal/firrtl/IR.scala')
| -rw-r--r-- | src/main/scala/Chisel/internal/firrtl/IR.scala | 12 |
1 files changed, 6 insertions, 6 deletions
diff --git a/src/main/scala/Chisel/internal/firrtl/IR.scala b/src/main/scala/Chisel/internal/firrtl/IR.scala index 5612f1af..7bb273c0 100644 --- a/src/main/scala/Chisel/internal/firrtl/IR.scala +++ b/src/main/scala/Chisel/internal/firrtl/IR.scala @@ -10,12 +10,12 @@ case class PrimOp(val name: String) { object PrimOp { val AddOp = PrimOp("add") - val AddModOp = PrimOp("addw") val SubOp = PrimOp("sub") - val SubModOp = PrimOp("subw") + val TailOp = PrimOp("tail") + val HeadOp = PrimOp("head") val TimesOp = PrimOp("mul") val DivideOp = PrimOp("div") - val ModOp = PrimOp("mod") + val RemOp = PrimOp("rem") val ShiftLeftOp = PrimOp("shl") val ShiftRightOp = PrimOp("shr") val DynamicShiftLeftOp = PrimOp("dshl") @@ -25,7 +25,6 @@ object PrimOp { val BitXorOp = PrimOp("xor") val BitNotOp = PrimOp("not") val ConcatOp = PrimOp("cat") - val BitSelectOp = PrimOp("bit") val BitsExtractOp = PrimOp("bits") val LessOp = PrimOp("lt") val LessEqOp = PrimOp("leq") @@ -148,13 +147,14 @@ abstract class Definition extends Command { def name: String = id.getRef.name } case class DefPrim[T <: Data](id: T, op: PrimOp, args: Arg*) extends Definition +case class DefInvalid(arg: Arg) extends Command case class DefWire(id: Data) extends Definition -case class DefRegister(id: Data, clock: Arg, reset: Arg, init: Arg) extends Definition +case class DefReg(id: Data, clock: Arg) extends Definition +case class DefRegInit(id: Data, clock: Arg, reset: Arg, init: Arg) extends Definition case class DefMemory(id: HasId, t: Data, size: Int) extends Definition case class DefSeqMemory(id: HasId, t: Data, size: Int) extends Definition case class DefMemPort[T <: Data](id: T, source: Node, dir: MemPortDirection, index: Arg, clock: Arg) extends Definition case class DefInstance(id: Module, ports: Seq[Port]) extends Definition -case class DefPoison[T <: Data](id: T) extends Definition case class WhenBegin(pred: Arg) extends Command case class WhenEnd() extends Command case class Connect(loc: Node, exp: Arg) extends Command |