diff options
| author | Andrew Waterman | 2016-01-28 12:25:17 -0800 |
|---|---|---|
| committer | Andrew Waterman | 2016-01-28 12:25:17 -0800 |
| commit | a6cdcecb7920b661de09948609674b89f21b985f (patch) | |
| tree | 11fb062f11c784287a0c63f933a0e3d9f863b702 /src/main/scala/Chisel/internal/firrtl/Emitter.scala | |
| parent | ccc88bbd9d462f04fe1dd39327349aeea8de9d3c (diff) | |
| parent | f9977fb4e5508032c3e17d201f747e71a32b9311 (diff) | |
Merge branch 'master' into modrefactor
Diffstat (limited to 'src/main/scala/Chisel/internal/firrtl/Emitter.scala')
| -rw-r--r-- | src/main/scala/Chisel/internal/firrtl/Emitter.scala | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/src/main/scala/Chisel/internal/firrtl/Emitter.scala b/src/main/scala/Chisel/internal/firrtl/Emitter.scala index 0c5da829..c2391f97 100644 --- a/src/main/scala/Chisel/internal/firrtl/Emitter.scala +++ b/src/main/scala/Chisel/internal/firrtl/Emitter.scala @@ -11,8 +11,8 @@ private class Emitter(circuit: Circuit) { private def emit(e: Command, ctx: Component): String = e match { case e: DefPrim[_] => s"node ${e.name} = ${e.op.name}(${e.args.map(_.fullName(ctx)).reduce(_ + ", " + _)})" case e: DefWire => s"wire ${e.name} : ${e.id.toType}" - case e: DefPoison[_] => s"poison ${e.name} : ${e.id.toType}" - case e: DefRegister => s"reg ${e.name} : ${e.id.toType}, ${e.clock.fullName(ctx)}, ${e.reset.fullName(ctx)}, ${e.init.fullName(ctx)}" + case e: DefReg => s"reg ${e.name} : ${e.id.toType}, ${e.clock.fullName(ctx)}" + case e: DefRegInit => s"reg ${e.name} : ${e.id.toType}, ${e.clock.fullName(ctx)} with : (reset => (${e.reset.fullName(ctx)}, ${e.init.fullName(ctx)}))" case e: DefMemory => s"cmem ${e.name} : ${e.t.toType}[${e.size}]" case e: DefSeqMemory => s"smem ${e.name} : ${e.t.toType}[${e.size}]" case e: DefMemPort[_] => s"${e.dir} mport ${e.name} = ${e.source.fullName(ctx)}[${e.index.fullName(ctx)}], ${e.clock.fullName(ctx)}" @@ -20,6 +20,7 @@ private class Emitter(circuit: Circuit) { case e: BulkConnect => s"${e.loc1.fullName(ctx)} <- ${e.loc2.fullName(ctx)}" case e: Stop => s"stop(${e.clk.fullName(ctx)}, UInt<1>(1), ${e.ret})" case e: Printf => s"""printf(${e.clk.fullName(ctx)}, UInt<1>(1), "${e.format}"${e.ids.map(_.fullName(ctx)).fold(""){_ + ", " + _}})""" + case e: DefInvalid => s"${e.arg.fullName(ctx)} is invalid" case e: DefInstance => { val modName = moduleMap.get(e.id.name).get s"inst ${e.name} of $modName" |