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| author | Adam Izraelevitz | 2015-12-11 13:18:58 -0800 |
|---|---|---|
| committer | Adam Izraelevitz | 2015-12-11 13:18:58 -0800 |
| commit | 8582ab12c288d8177c8b4a8a6172b58691cc6430 (patch) | |
| tree | f8115324c12c54a3077517f5b6b997cc16951c64 /src/main/scala/Chisel/firrtl/IR.scala | |
| parent | 20951ecdbcb81c194ddcdd1e8241b1bdd647dd9f (diff) | |
| parent | 5859d231859c6a8b9c234e7a71cbc85e5d75f61b (diff) | |
Merge pull request #65 from ucb-bar/asserts
Add support for printf and asserts, add testbench for asserts and printf
Diffstat (limited to 'src/main/scala/Chisel/firrtl/IR.scala')
| -rw-r--r-- | src/main/scala/Chisel/firrtl/IR.scala | 2 |
1 files changed, 2 insertions, 0 deletions
diff --git a/src/main/scala/Chisel/firrtl/IR.scala b/src/main/scala/Chisel/firrtl/IR.scala index 458e6ac5..8cc31b54 100644 --- a/src/main/scala/Chisel/firrtl/IR.scala +++ b/src/main/scala/Chisel/firrtl/IR.scala @@ -151,6 +151,8 @@ case class WhenEnd() extends Command case class Connect(loc: Node, exp: Arg) extends Command case class BulkConnect(loc1: Node, loc2: Node) extends Command case class ConnectInit(loc: Node, exp: Arg) extends Command +case class Stop(clk: Arg, ret: Int) extends Command +case class Printf(clk: Arg, format: String, ids: Seq[Arg]) extends Command case class Component(id: Module, name: String, ports: Seq[Port], commands: Seq[Command]) extends Arg case class Port(id: Data, dir: Direction) |