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| author | Andrew Waterman | 2015-07-28 19:13:39 -0700 |
|---|---|---|
| committer | Andrew Waterman | 2015-07-28 19:13:39 -0700 |
| commit | 874d830788721f270643aead3c09b86d2c3c7e9d (patch) | |
| tree | 45a95b27683f1de0dcc86d9da95f8a4562398a09 /src/main/scala/Chisel/Tester.scala | |
| parent | 3a8f37a211a8018f967e7a34143dd057904b2707 (diff) | |
Dead code elimination
Diffstat (limited to 'src/main/scala/Chisel/Tester.scala')
| -rw-r--r-- | src/main/scala/Chisel/Tester.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/Chisel/Tester.scala b/src/main/scala/Chisel/Tester.scala index cf7c7b1c..37923a5f 100644 --- a/src/main/scala/Chisel/Tester.scala +++ b/src/main/scala/Chisel/Tester.scala @@ -178,7 +178,7 @@ class ManualTester[+T <: Module] cmd = "wire_peek " + name; } val s = emulatorCmd(cmd) - val rv = toLitVal(s) + val rv = BigInt(s.substring(2), 16) if (isTrace) println(" PEEK " + name + " " + (if (off >= 0) (off + " ") else "") + "-> " + s) rv } |