Remove dependences from Chisel core on Chisel utils

Partially resolves #164

1 files changed, 47 insertions, 0 deletions

diff --git a/src/main/scala/Chisel/SeqUtils.scala b/src/main/scala/Chisel/SeqUtils.scala
new file mode 100644
index 00000000..c63f5735
--- /dev/null
+++ b/src/main/scala/Chisel/SeqUtils.scala
@@ -0,0 +1,47 @@
+// See LICENSE for license details.
+
+package Chisel
+
+private[Chisel] object SeqUtils {
+  /** Equivalent to Cat(r(n-1), ..., r(0)) */
+  def asUInt[T <: Bits](in: Seq[T]): UInt = {
+    if (in.tail.isEmpty) {
+      in.head.asUInt
+    } else {
+      val left = asUInt(in.slice(0, in.length/2))
+      val right = asUInt(in.slice(in.length/2, in.length))
+      right ## left
+    }
+  }
+
+  /** Counts the number of true Bools in a Seq */
+  def count(in: Seq[Bool]): UInt = {
+    if (in.size == 0) {
+      UInt(0)
+    } else if (in.size == 1) {
+      in.head
+    } else {
+      count(in.slice(0, in.size/2)) + (UInt(0) ## count(in.slice(in.size/2, in.size)))
+    }
+  }
+
+  /** Returns data value corresponding to first true predicate */
+  def priorityMux[T <: Bits](in: Seq[(Bool, T)]): T = {
+    if (in.size == 1) {
+      in.head._2
+    } else {
+      Mux(in.head._1, in.head._2, priorityMux(in.tail))
+    }
+  }
+
+  /** Returns data value corresponding to lone true predicate */
+  def oneHotMux[T <: Data](in: Iterable[(Bool, T)]): T = {
+    if (in.tail.isEmpty) {
+      in.head._2
+    } else {
+      val masked = for ((s, i) <- in) yield Mux(s, i.toBits, Bits(0))
+      val width = in.map(_._2.width).reduce(_ max _)
+      in.head._2.cloneTypeWidth(width).fromBits(masked.reduceLeft(_|_))
+    }
+  }
+}