Merge branch 'sdtwigg_rebase_renamechisel3' into sdtwigg_wrap_renamechisel3

1 files changed, 0 insertions, 17 deletions

diff --git a/src/main/scala/Chisel/Main.scala b/src/main/scala/Chisel/Main.scala
deleted file mode 100644
index a72debc3..00000000
--- a/src/main/scala/Chisel/Main.scala
+++ /dev/null
@@ -1,17 +0,0 @@
-// See LICENSE for license details.
-
-package Chisel
-
-import java.io.File
-
-@deprecated("chiselMain doesn't exist in Chisel3", "3.0") object chiselMain {
-  def apply[T <: Module](args: Array[String], gen: () => T): Unit =
-    Predef.assert(false, "No more chiselMain in Chisel3")
-
-  def run[T <: Module] (args: Array[String], gen: () => T): Unit = {
-    val circuit = Driver.elaborate(gen)
-    Driver.parseArgs(args)
-    val output_file = new File(Driver.targetDir + "/" + circuit.name + ".fir")
-    Driver.dumpFirrtl(circuit, Option(output_file))
-  }
-}