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authorAndrew Waterman2016-02-03 23:51:06 -0800
committerAndrew Waterman2016-02-03 23:51:06 -0800
commitc5240a3bfe1c05a206c7c34c3c7c5007bbcc3680 (patch)
tree89893f19fba9aacc7e18ba8013b428e9f1e03482 /src/main/scala/Chisel/Main.scala
parent898efea92e9e13775b39dd7fb92cac420334b9c9 (diff)
parent7fc2ea6a14da441db9c47d094361fea07436f6d3 (diff)
Merge branch 'master' into blackbox
Diffstat (limited to 'src/main/scala/Chisel/Main.scala')
-rw-r--r--src/main/scala/Chisel/Main.scala8
1 files changed, 8 insertions, 0 deletions
diff --git a/src/main/scala/Chisel/Main.scala b/src/main/scala/Chisel/Main.scala
index 23abc763..750e8712 100644
--- a/src/main/scala/Chisel/Main.scala
+++ b/src/main/scala/Chisel/Main.scala
@@ -2,7 +2,15 @@
package Chisel
+import java.io.File
+
@deprecated("chiselMain doesn't exist in Chisel3", "3.0") object chiselMain {
def apply[T <: Module](args: Array[String], gen: () => T) =
Predef.assert(false)
+
+ def run[T <: Module] (args: Array[String], gen: () => T) = {
+ def circuit = Driver.elaborate(gen)
+ def output_file = new File(Driver.targetDir + "/" + circuit.name + ".fir")
+ Driver.dumpFirrtl(circuit, Option(output_file))
+ }
}