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authorchick2016-03-08 09:31:59 -0800
committerchick2016-03-08 09:31:59 -0800
commitdb0236c0363e8c1dee8c49759a79a8448711ed2b (patch)
treec96e134c311de04466025bd8123b8cad877c219a /src/main/scala/Chisel/Main.scala
parentb2395b44257e14e5acfd1209076736c3e9974e21 (diff)
parent315efd3809454637a6d56958929c7c44943d8812 (diff)
Merge branch 'master' of https://github.com/ucb-bar/chisel3
Diffstat (limited to 'src/main/scala/Chisel/Main.scala')
-rw-r--r--src/main/scala/Chisel/Main.scala1
1 files changed, 1 insertions, 0 deletions
diff --git a/src/main/scala/Chisel/Main.scala b/src/main/scala/Chisel/Main.scala
index 750e8712..349f8b18 100644
--- a/src/main/scala/Chisel/Main.scala
+++ b/src/main/scala/Chisel/Main.scala
@@ -11,6 +11,7 @@ import java.io.File
def run[T <: Module] (args: Array[String], gen: () => T) = {
def circuit = Driver.elaborate(gen)
def output_file = new File(Driver.targetDir + "/" + circuit.name + ".fir")
+ Driver.parseArgs(args)
Driver.dumpFirrtl(circuit, Option(output_file))
}
}