diff options
| author | ducky | 2015-10-30 14:53:17 -0700 |
|---|---|---|
| committer | ducky | 2015-10-30 14:53:17 -0700 |
| commit | 78dd6b801f0988c381f47c76ca23b58f17eee942 (patch) | |
| tree | 433a8b174c1410a209cdf185676adca9fa559169 /src/main/scala/Chisel/Cat.scala | |
| parent | 22127c79c872ebcf5da50858c7309ad82d39eb63 (diff) | |
Move Cat into utils
Diffstat (limited to 'src/main/scala/Chisel/Cat.scala')
| -rw-r--r-- | src/main/scala/Chisel/Cat.scala | 31 |
1 files changed, 0 insertions, 31 deletions
diff --git a/src/main/scala/Chisel/Cat.scala b/src/main/scala/Chisel/Cat.scala deleted file mode 100644 index 8075c11d..00000000 --- a/src/main/scala/Chisel/Cat.scala +++ /dev/null @@ -1,31 +0,0 @@ -// See LICENSE for license details. - -package Chisel -import Builder.pushOp -import PrimOp._ - -// REVIEW TODO: Should the FIRRTL emission be part of Bits, with a separate -// Cat in stdlib that can do a reduction among multiple elements? -object Cat { - /** Combine data elements together - * @param a Data to combine with - * @param r any number of other Data elements to be combined in order - * @return A UInt which is all of the bits combined together - */ - def apply[T <: Bits](a: T, r: T*): UInt = apply(a :: r.toList) - - /** Combine data elements together - * @param r any number of other Data elements to be combined in order - * @return A UInt which is all of the bits combined together - */ - def apply[T <: Bits](r: Seq[T]): UInt = { - if (r.tail.isEmpty) { - r.head.asUInt - } else { - val left = apply(r.slice(0, r.length/2)) - val right = apply(r.slice(r.length/2, r.length)) - val w = left.width + right.width - pushOp(DefPrim(UInt(w), ConcatOp, left.ref, right.ref)) - } - } -} |
