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authorJim Lawson2015-07-24 17:17:01 -0700
committerJim Lawson2015-07-24 17:17:01 -0700
commite73450165c59d68b524689a7169e03140a41a1c5 (patch)
treeb7236f80d9abf60775ecbcefe6f7ca25557dce73 /src/main/scala/Chisel/Backend.scala
parent94893bad972ded686a2c68dd334aa40b92e3b85d (diff)
parent3976145bb8c7595ad0f0a7fbb4ccbbd3030d8873 (diff)
Merge pull request #1 from ucb-bar/packagedir
Packagedir
Diffstat (limited to 'src/main/scala/Chisel/Backend.scala')
-rw-r--r--src/main/scala/Chisel/Backend.scala10
1 files changed, 10 insertions, 0 deletions
diff --git a/src/main/scala/Chisel/Backend.scala b/src/main/scala/Chisel/Backend.scala
new file mode 100644
index 00000000..9b8bfb6d
--- /dev/null
+++ b/src/main/scala/Chisel/Backend.scala
@@ -0,0 +1,10 @@
+package Chisel
+import Chisel._
+
+class Backend;
+class FloBackend extends Backend;
+class CppBackend extends Backend;
+class VerilogBackend extends Backend;
+class FPGABackend extends Backend;
+class DotBackend extends Backend;
+class SysCBackend extends Backend;