[docs] Remove body from minimizing output bits recipe (#2290)

Remove the body from the emitted Verilog. This was the original intent
of the example, and it avoids an issue where Jekyll was not able to
render the Markdown file due to Verilog concatenation looking like a
variable escape.

1 files changed, 3 insertions, 0 deletions

diff --git a/docs/src/cookbooks/cookbook.md b/docs/src/cookbooks/cookbook.md
index e23b158c..d4cf3030 100644
--- a/docs/src/cookbooks/cookbook.md
+++ b/docs/src/cookbooks/cookbook.md
@@ -431,6 +431,9 @@ Unlike `Vecs` which represent a singular Chisel type and must have the same widt
 
 ```scala mdoc:verilog
 chisel3.stage.ChiselStage.emitVerilog(new CountBits(4))
+  // remove the body of the module by removing everything after ');'
+  .split("\\);")
+  .head + ");\n"
 ```
 
 ## Predictable Naming