Merge pull request #1745 from chipsalliance/remove-val-io

Remove "val io" and rename MultiIOModule to Module

1 files changed, 3 insertions, 4 deletions

diff --git a/docs/src/wiki-deprecated/ports.md b/docs/src/wiki-deprecated/ports.md
index f8c30b7a..251ce243 100644
--- a/docs/src/wiki-deprecated/ports.md
+++ b/docs/src/wiki-deprecated/ports.md
@@ -30,21 +30,20 @@ provide powerful wiring constructs described later.
 
 (Chisel 3.2+)
 
-Chisel 3.2+ introduces an API `DataMirror.modulePorts` which can be used to inspect the IOs of any Chisel module, including MultiIOModules, RawModules, and BlackBoxes.
-
+Chisel 3.2 introduced `DataMirror.modulePorts` which can be used to inspect the IOs of any Chisel module (this includes modules in both `import chisel3._` and `import Chisel._`, as well as BlackBoxes from each package).
 Here is an example of how to use this API:
 
 ```scala
 import chisel3.experimental.DataMirror
 
-class Adder extends MultiIOModule {
+class Adder extends Module {
   val a = IO(Input(UInt(8.W)))
   val b = IO(Input(UInt(8.W)))
   val c = IO(Output(UInt(8.W)))
   c := a +& b
 }
 
-class Test extends MultiIOModule {
+class Test extends Module {
   val adder = Module(new Adder)
   // for debug only
   adder.a := DontCare