diff options
| author | Verneri Hirvonen | 2021-07-08 18:59:12 +0300 |
|---|---|---|
| committer | GitHub | 2021-07-08 15:59:12 +0000 |
| commit | bb520b8573328fda5f7b3c3892e6995fbe1b4239 (patch) | |
| tree | 3c2280100553ddab64b23e9e41baa0c34ff7950a /docs/src/explanations/chisel-enum.md | |
| parent | f1e37900170124254f3cf4599a45e7a485c17a91 (diff) | |
Add `isOneOf` method to `ChiselEnum` (#1966)
* Add @ekiwi's code as a starting point
* Add test for ChiselEnum isOneOf method
* Make isOneOfTester naming consistent with other testers
* Add scaladoc comments for isOneOf
* Add isOneOf tests that use the method that takes variable number of args
* Add guide level documentation example for isOneOf
Diffstat (limited to 'docs/src/explanations/chisel-enum.md')
| -rw-r--r-- | docs/src/explanations/chisel-enum.md | 19 |
1 files changed, 19 insertions, 0 deletions
diff --git a/docs/src/explanations/chisel-enum.md b/docs/src/explanations/chisel-enum.md index 96fc9e8a..a390aea4 100644 --- a/docs/src/explanations/chisel-enum.md +++ b/docs/src/explanations/chisel-enum.md @@ -182,6 +182,25 @@ def expectedSel(sel: AluMux1Sel.Type): Boolean = sel match { } ``` +The enum value type also defines some convenience methods for working with `ChiselEnum` values. For example, continuing with the RISC-V opcode +example, one could easily create hardware signal that is only asserted on LOAD/STORE operations (when the enum value is equal to `Opcode.load` +or `Opcode.store`) using the `.isOneOf` method: + +```scala mdoc +class LoadStoreExample extends Module { + val io = IO(new Bundle { + val opcode = Input(Opcode()) + val load_or_store = Output(Bool()) + }) + io.load_or_store := io.opcode.isOneOf(Opcode.load, Opcode.store) +} +``` + +```scala mdoc:invisible +// Always need to run Chisel to see if there are elaboration errors +ChiselStage.emitVerilog(new LoadStoreExample) +``` + Some additional useful methods defined on the `ChiselEnum` object are: * `.all`: returns the enum values within the enumeration |
