cleanup

5 files changed, 58 insertions, 58 deletions

diff --git a/core/src/main/scala/chisel3/Module.scala b/core/src/main/scala/chisel3/Module.scala
index a2d5cec6..63bf9129 100644
--- a/core/src/main/scala/chisel3/Module.scala
+++ b/core/src/main/scala/chisel3/Module.scala
@@ -147,7 +147,7 @@ object Module extends SourceInfoDoc {
   *
   * @note Module instantiations must be wrapped in a Module() call.
   */
-abstract class Module(implicit moduleCompileOptions: CompileOptions) extends RawModule {
+abstract class Module[T](implicit moduleCompileOptions: CompileOptions) extends RawModule {
   // Implicit clock and reset pins
   final val clock: Clock = IO(Input(Clock())).suggestName("clock")
   final val reset: Reset = IO(Input(mkReset)).suggestName("reset")
@@ -394,10 +394,10 @@ package internal {
         // FIXME This almost certainly doesn't work since clonePorts is not a real thing...
         pushCommand(DefInvalid(sourceInfo, clonePorts.ref))
       }
-      if (proto.isInstanceOf[Module]) {
-        clonePorts("clock") := Module.clock
-        clonePorts("reset") := Module.reset
-      }
+      // if (proto.isInstanceOf[Module]) {
+      //   clonePorts("clock") := Module.clock
+      //   clonePorts("reset") := Module.reset
+      // }
       clonePorts
     }
   }
diff --git a/core/src/main/scala/chisel3/RawModule.scala b/core/src/main/scala/chisel3/RawModule.scala
index 9668313a..717fd33c 100644
--- a/core/src/main/scala/chisel3/RawModule.scala
+++ b/core/src/main/scala/chisel3/RawModule.scala
@@ -173,11 +173,11 @@ abstract class RawModule(implicit moduleCompileOptions: CompileOptions) extends
   }
 }
 
-trait RequireAsyncReset extends Module {
+trait RequireAsyncReset extends Module[Any] {
   override private[chisel3] def mkReset: AsyncReset = AsyncReset()
 }
 
-trait RequireSyncReset extends Module {
+trait RequireSyncReset extends Module[Any] {
   override private[chisel3] def mkReset: Bool = Bool()
 }
 
diff --git a/core/src/main/scala/chisel3/aop/Aspect.scala b/core/src/main/scala/chisel3/aop/Aspect.scala
index dd014357..d5499946 100644
--- a/core/src/main/scala/chisel3/aop/Aspect.scala
+++ b/core/src/main/scala/chisel3/aop/Aspect.scala
@@ -1,47 +1,47 @@
-// SPDX-License-Identifier: Apache-2.0
-
-package chisel3.aop
-
-import chisel3.RawModule
-import firrtl.annotations.{Annotation, NoTargetAnnotation}
-import firrtl.options.Unserializable
-import firrtl.AnnotationSeq
-
-/** Represents an aspect of a Chisel module, by specifying
-  * what behavior should be done to instance, via the FIRRTL Annotation Mechanism
-  * @tparam T Type of top-level module
-  */
-abstract class Aspect[T <: RawModule] extends Annotation with Unserializable with NoTargetAnnotation {
-
-  /** variable to save [[AnnotationSeq]] from [[chisel3.stage.phases.AspectPhase]]
-    * to be used at [[chisel3.aop.injecting.InjectorAspect]], exposes annotations to [[chisel3.internal.DynamicContext]]
-    */
-  private[aop] var annotationsInAspect: AnnotationSeq = Seq()
-
-  /** Convert this Aspect to a seq of FIRRTL annotation
-    * @param top
-    * @return
-    */
-  def toAnnotation(top: T): AnnotationSeq
-
-  /** Called by [[chisel3.stage.phases.AspectPhase]] to resolve this Aspect into annotations
-    * @param top
-    * @return
-    */
-  private[chisel3] def resolveAspect(top: RawModule, remainingAnnotations: AnnotationSeq): AnnotationSeq = {
-    annotationsInAspect = remainingAnnotations
-    toAnnotation(top.asInstanceOf[T])
-  }
-}
-
-/** Holds utility functions for Aspect stuff */
-object Aspect {
-
-  /** Converts elaborated Chisel components to FIRRTL modules
-    * @param chiselIR
-    * @return
-    */
-  def getFirrtl(chiselIR: chisel3.internal.firrtl.Circuit): firrtl.ir.Circuit = {
-    chisel3.internal.firrtl.Converter.convert(chiselIR)
-  }
-}
+// // SPDX-License-Identifier: Apache-2.0
+
+// package chisel3.aop
+
+// import chisel3.RawModule
+// import firrtl.annotations.{Annotation, NoTargetAnnotation}
+// import firrtl.options.Unserializable
+// import firrtl.AnnotationSeq
+
+// /** Represents an aspect of a Chisel module, by specifying
+//   * what behavior should be done to instance, via the FIRRTL Annotation Mechanism
+//   * @tparam T Type of top-level module
+//   */
+// abstract class Aspect[T <: RawModule] extends Annotation with Unserializable with NoTargetAnnotation {
+
+//   /** variable to save [[AnnotationSeq]] from [[chisel3.stage.phases.AspectPhase]]
+//     * to be used at [[chisel3.aop.injecting.InjectorAspect]], exposes annotations to [[chisel3.internal.DynamicContext]]
+//     */
+//   private[aop] var annotationsInAspect: AnnotationSeq = Seq()
+
+//   /** Convert this Aspect to a seq of FIRRTL annotation
+//     * @param top
+//     * @return
+//     */
+//   def toAnnotation(top: T): AnnotationSeq
+
+//   /** Called by [[chisel3.stage.phases.AspectPhase]] to resolve this Aspect into annotations
+//     * @param top
+//     * @return
+//     */
+//   private[chisel3] def resolveAspect(top: RawModule, remainingAnnotations: AnnotationSeq): AnnotationSeq = {
+//     annotationsInAspect = remainingAnnotations
+//     toAnnotation(top.asInstanceOf[T])
+//   }
+// }
+
+// /** Holds utility functions for Aspect stuff */
+// object Aspect {
+
+//   /** Converts elaborated Chisel components to FIRRTL modules
+//     * @param chiselIR
+//     * @return
+//     */
+//   def getFirrtl(chiselIR: chisel3.internal.firrtl.Circuit): firrtl.ir.Circuit = {
+//     chisel3.internal.firrtl.Converter.convert(chiselIR)
+//   }
+// }
diff --git a/core/src/main/scala/chisel3/experimental/Trace.scala b/core/src/main/scala/chisel3/experimental/Trace.scala
index eb2ed46a..a31cef10 100644
--- a/core/src/main/scala/chisel3/experimental/Trace.scala
+++ b/core/src/main/scala/chisel3/experimental/Trace.scala
@@ -23,7 +23,7 @@ object Trace {
 
   /** Trace a Instance name. */
   @deprecated("switch to traceNameV2 (until Chisel 3.6)", "3.5.5")
-  def traceName(x: Module): Unit = traceName(x: RawModule)
+  def traceName(x: Module[Any]): Unit = traceName(x: RawModule)
 
   /** Trace a Instance name. */
   @deprecated("switch to traceNameV2 (until Chisel 3.6)", "3.5.5")
diff --git a/core/src/main/scala/chisel3/package.scala b/core/src/main/scala/chisel3/package.scala
index afffad1c..bd279914 100644
--- a/core/src/main/scala/chisel3/package.scala
+++ b/core/src/main/scala/chisel3/package.scala
@@ -209,8 +209,8 @@ package object chisel3 {
 
   type InstanceId = internal.InstanceId
 
-  @deprecated("MultiIOModule is now just Module", "Chisel 3.5")
-  type MultiIOModule = chisel3.Module
+  // @deprecated("MultiIOModule is now just Module", "Chisel 3.5")
+  // type MultiIOModule = chisel3.Module[Any]
 
   /** Implicit for custom Printable string interpolator */
   implicit class PrintableHelper(val sc: StringContext) extends AnyVal {
@@ -367,7 +367,7 @@ package object chisel3 {
     "duplicated with DataMirror.fullModulePorts, this returns an internal API, will be removed in Chisel 3.6",
     "Chisel 3.5"
   )
-  def getModulePorts(m: Module): Seq[Port] = m.getPorts
+  def getModulePorts(m: Module[Any]): Seq[Port] = m.getPorts
 
   class BindingException(message: String) extends ChiselException(message)