Move methods to library

2 files changed, 11 insertions, 7 deletions

diff --git a/core/src/main/scala/chisel3/AbstractModule.scala b/core/src/main/scala/chisel3/AbstractModule.scala
index 7c4be632..61cad9c2 100644
--- a/core/src/main/scala/chisel3/AbstractModule.scala
+++ b/core/src/main/scala/chisel3/AbstractModule.scala
@@ -9,19 +9,22 @@ import chisel3.internal.Builder._
 import chisel3.internal.firrtl._
 import chisel3.experimental.BaseModule
 
-class AbstractInterface[T <: Data](params: T) {
-  println(params)
-  val ioNode = IO(params)
+case class AbstractInterface[T](params: T)
+
+case class Interface(ifaceContainer: AbstractInterface[_]*)
+
+class Op[A, B, C](func: A => B => C) {
+  val f: A => B => C = func
 }
 
 /**
   A module that uses types from its metaconnects to type its IOs. 
   */
 class AbstractModule(iface: Seq[AbstractInterface[_]]) extends BaseModule {
-  iface.foreach(x => {
-    println(x, x.ioNode)
-  })
-  println(iface)
+  // iface.foreach(x => {
+  //   // println(x, x.ioNode)
+  // })
+  // println(iface)
   def generateComponent(): Option[chisel3.internal.firrtl.Component] = ???
   def initializeInParent(parentCompileOptions: chisel3.CompileOptions): Unit = ???
 }
diff --git a/core/src/main/scala/chisel3/MetaConnect.scala b/core/src/main/scala/chisel3/MetaConnect.scala
index 0f338e6c..acaef86f 100644
--- a/core/src/main/scala/chisel3/MetaConnect.scala
+++ b/core/src/main/scala/chisel3/MetaConnect.scala
@@ -6,4 +6,5 @@ object MetaConnect {
       f(that)(me)
     }
   }
+  implicit def abstractInterfaceConnection[A, B, C](implicit f: A => B => C): AbstractInterface[A] => AbstractInterface[B] => AbstractInterface[C] = (a: AbstractInterface[A]) => (b: AbstractInterface[B]) => new AbstractInterface(f(a.params)(b.params))
 }