diff options
| author | mergify[bot] | 2022-11-05 22:31:07 +0000 |
|---|---|---|
| committer | GitHub | 2022-11-05 22:31:07 +0000 |
| commit | 017bd6b9c96974df2a3c4f35e069d60fec001f2e (patch) | |
| tree | 8dab4e44284af8a0904f0817c1875a9b73243328 /core/src | |
| parent | 4149157df6531d124483d992daf96cf4e62a0f0c (diff) | |
Support Analog in DataView (#2782) (#2828)
Co-authored-by: Megan Wachs <megan@sifive.com>
(cherry picked from commit 26100a875c69bf56f7442fac82ca9c74ad3596eb)
Co-authored-by: Jack Koenig <koenig@sifive.com>
Diffstat (limited to 'core/src')
| -rw-r--r-- | core/src/main/scala/chisel3/Data.scala | 1 | ||||
| -rw-r--r-- | core/src/main/scala/chisel3/experimental/Analog.scala | 3 | ||||
| -rw-r--r-- | core/src/main/scala/chisel3/experimental/Attach.scala (renamed from core/src/main/scala/chisel3/Attach.scala) | 0 |
3 files changed, 3 insertions, 1 deletions
diff --git a/core/src/main/scala/chisel3/Data.scala b/core/src/main/scala/chisel3/Data.scala index f52f99de..52cc041c 100644 --- a/core/src/main/scala/chisel3/Data.scala +++ b/core/src/main/scala/chisel3/Data.scala @@ -684,6 +684,7 @@ abstract class Data extends HasId with NamedComponent with SourceInfoDoc { topBindingOpt match { case Some(binding: ReadOnlyBinding) => throwException(s"internal error: attempted to generate LHS ref to ReadOnlyBinding $binding") + case Some(ViewBinding(target)) => reify(target).lref case Some(binding: TopBinding) => Node(this) case opt => throwException(s"internal error: unknown binding $opt in generating LHS ref") } diff --git a/core/src/main/scala/chisel3/experimental/Analog.scala b/core/src/main/scala/chisel3/experimental/Analog.scala index a366f0c3..7d89025c 100644 --- a/core/src/main/scala/chisel3/experimental/Analog.scala +++ b/core/src/main/scala/chisel3/experimental/Analog.scala @@ -69,7 +69,8 @@ final class Analog private (private[chisel3] val width: Width) extends Element { } targetTopBinding match { - case _: WireBinding | _: PortBinding => direction = ActualDirection.Bidirectional(ActualDirection.Default) + case _: WireBinding | _: PortBinding | _: ViewBinding | _: AggregateViewBinding => + direction = ActualDirection.Bidirectional(ActualDirection.Default) case x => throwException(s"Analog can only be Ports and Wires, not '$x'") } binding = target diff --git a/core/src/main/scala/chisel3/Attach.scala b/core/src/main/scala/chisel3/experimental/Attach.scala index 5c9cfe53..5c9cfe53 100644 --- a/core/src/main/scala/chisel3/Attach.scala +++ b/core/src/main/scala/chisel3/experimental/Attach.scala |