Merge pull request #2246 from chipsalliance/scalafmt

Add scalafmt configuration and apply it.

1 files changed, 3 insertions, 3 deletions

diff --git a/core/src/main/scala/chisel3/BoolFactory.scala b/core/src/main/scala/chisel3/BoolFactory.scala
index 787f1e5e..1d96659f 100644
--- a/core/src/main/scala/chisel3/BoolFactory.scala
+++ b/core/src/main/scala/chisel3/BoolFactory.scala
@@ -4,14 +4,14 @@ package chisel3
 
 import chisel3.internal.firrtl.{ULit, Width}
 
-
 trait BoolFactory {
+
   /** Creates an empty Bool.
-   */
+    */
   def apply(): Bool = new Bool()
 
   /** Creates Bool literal.
-   */
+    */
   protected[chisel3] def Lit(x: Boolean): Bool = {
     val result = new Bool()
     val lit = ULit(if (x) 1 else 0, Width(1))