Merge branch 'master' into add-asbool-to-clock

1 files changed, 2 insertions, 2 deletions

diff --git a/chiselFrontend/src/main/scala/chisel3/Reg.scala b/chiselFrontend/src/main/scala/chisel3/Reg.scala
index 51c59bdb..a3e6b2a0 100644
--- a/chiselFrontend/src/main/scala/chisel3/Reg.scala
+++ b/chiselFrontend/src/main/scala/chisel3/Reg.scala
@@ -108,13 +108,13 @@ object RegNext {
   * val x = Wire(UInt())
   * val y = Wire(UInt(8.W))
   * val r1 = RegInit(x) // width will be inferred
-  * val r2 = RegInit(y) // width will be inferred
+  * val r2 = RegInit(y) // width is set to 8
   * }}}
   *
   * 3. [[Aggregate]] initializer - width will be set to match the aggregate
   *
   * {{{
-  * class MyBundle {
+  * class MyBundle extends Bundle {
   *   val unknown = UInt()
   *   val known   = UInt(8.W)
   * }