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| author | Richard Lin | 2016-05-20 16:34:03 -0700 |
|---|---|---|
| committer | Richard Lin | 2016-05-20 16:34:03 -0700 |
| commit | d742d70a05b5fa997517ea7b5eb2d15b23e7a431 (patch) | |
| tree | 3c2453014c78e889fd1502085661ed604c5f0b34 /chiselFrontend/src/main/scala/Chisel/BlackBox.scala | |
| parent | d7697eb14a0195cc3726bf45fdf38c631b6f6507 (diff) | |
| parent | e92f2f69477a6ce86fc148a1a95db5797f2e3051 (diff) | |
Merge pull request #186 from ucb-bar/sloc_impl
Source locators
Diffstat (limited to 'chiselFrontend/src/main/scala/Chisel/BlackBox.scala')
| -rw-r--r-- | chiselFrontend/src/main/scala/Chisel/BlackBox.scala | 5 |
1 files changed, 3 insertions, 2 deletions
diff --git a/chiselFrontend/src/main/scala/Chisel/BlackBox.scala b/chiselFrontend/src/main/scala/Chisel/BlackBox.scala index be72934d..b634f021 100644 --- a/chiselFrontend/src/main/scala/Chisel/BlackBox.scala +++ b/chiselFrontend/src/main/scala/Chisel/BlackBox.scala @@ -4,6 +4,7 @@ package Chisel import internal.Builder.pushCommand import internal.firrtl.{ModuleIO, DefInvalid} +import internal.sourceinfo.SourceInfo /** Defines a black box, which is a module that can be referenced from within * Chisel, but is not defined in the emitted Verilog. Useful for connecting @@ -39,10 +40,10 @@ abstract class BlackBox extends Module { // Don't setup clock, reset // Cann't invalide io in one bunch, must invalidate each part separately - override private[Chisel] def setupInParent(): this.type = _parent match { + override private[Chisel] def setupInParent(implicit sourceInfo: SourceInfo): this.type = _parent match { case Some(p) => { // Just init instance inputs - for((_,port) <- ports) pushCommand(DefInvalid(port.ref)) + for((_,port) <- ports) pushCommand(DefInvalid(sourceInfo, port.ref)) this } case None => this |