diff options
| author | Aditya Naik | 2024-03-07 09:26:46 -0800 |
|---|---|---|
| committer | Aditya Naik | 2024-03-07 09:26:46 -0800 |
| commit | 7e16bac1a2d7caf9f38c3934eab7bf0db982a312 (patch) | |
| tree | 4a0505e87385889746f30889b5f37592be5fd047 /AbstractModule.scala | |
| parent | 6a132a490c280684fd27f09a3af2249faf4d13d1 (diff) | |
Move methods to library
Diffstat (limited to 'AbstractModule.scala')
| -rw-r--r-- | AbstractModule.scala | 58 |
1 files changed, 29 insertions, 29 deletions
diff --git a/AbstractModule.scala b/AbstractModule.scala index 103d598f..3f6e117f 100644 --- a/AbstractModule.scala +++ b/AbstractModule.scala @@ -1,36 +1,36 @@ -package chiselTests +// package chiselTests -import chisel3._ -import chisel3.stage.ChiselStage -import chisel3.MetaConnect._ +// import chisel3._ +// import chisel3.stage.ChiselStage +// import chisel3.MetaConnect._ -object TypeArithmetic { - // implicit val f1: UInt => UInt => UInt = (a: UInt) => (b: UInt) => Mux(a > b, a, b) - implicit val f2: SomeTypeContainer => UInt => SomeTypeContainer = (a: SomeTypeContainer) => (b: UInt) => new SomeTypeContainer(b.litValue.toInt+a.w) -} +// object TypeArithmetic { +// // implicit val f1: UInt => UInt => UInt = (a: UInt) => (b: UInt) => Mux(a > b, a, b) +// implicit val f2: SomeTypeContainer => UInt => SomeTypeContainer = (a: SomeTypeContainer) => (b: UInt) => new SomeTypeContainer(b.litValue.toInt+a.w) +// } -case class SomeTypeContainer(w: Int) extends UInt(w.W) +// case class SomeTypeContainer(w: Int) extends UInt(w.W) -class AbstractModuleContainer extends AbstractModule({ - val mod1 = new AbstractInterface[UInt](Input(UInt(4.W))) - val mod2 = new AbstractInterface[UInt](Output(UInt(8.W))) - val mod3 = new AbstractInterface[SomeTypeContainer](Output(SomeTypeContainer(16))) +// class AbstractModuleContainer extends AbstractModule({ +// val mod1 = new AbstractInterface[UInt](Input(UInt(4.W))) +// val mod2 = new AbstractInterface[UInt](Output(UInt(8.W))) +// val mod3 = new AbstractInterface[SomeTypeContainer](Output(SomeTypeContainer(16))) - import TypeArithmetic._ - val typeA = mod3.ioNode.makeConnection(mod2.ioNode) - // val typeB = mod2.ioNode.makeConnection(mod3.ioNode) - // println(s"\ttypeA: ${typeA}\n\ttypeB: ${typeB}") - // need to create versions of mods1-3 with these new type params - // similar to log aggregation writer monad? but more like type aggregation - Seq(mod1, mod2, mod3) -}) +// // import TypeArithmetic._ +// // val typeA = mod3.ioNode.makeConnection(mod2.ioNode) +// // // val typeB = mod2.ioNode.makeConnection(mod3.ioNode) +// // // println(s"\ttypeA: ${typeA}\n\ttypeB: ${typeB}") +// // // need to create versions of mods1-3 with these new type params +// // // similar to log aggregation writer monad? but more like type aggregation +// // Seq(mod1, mod2, mod3) +// }) -class LowerableModule extends Module { - val innerModule = Module(new AbstractModuleContainer) -} +// class LowerableModule extends Module { +// val innerModule = Module(new AbstractModuleContainer) +// } -object main { - def main(args: Array[String]): Unit = { - println(chisel3.stage.ChiselStage.emitChirrtl(new LowerableModule)) - } -} +// object main { +// def main(args: Array[String]): Unit = { +// println(chisel3.stage.ChiselStage.emitChirrtl(new LowerableModule)) +// } +// } |
