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authorAditya Naik2024-01-02 11:29:49 -0800
committerAditya Naik2024-01-02 11:29:49 -0800
commit7a3a5a07e9e340e11f8b7cb6a53c1f52f4e4d3a1 (patch)
treeb84e0940f0a3827cb938b81cce9187ce71f3e747 /AbstractModule.scala
parent7fc39a02a806bfb74c78147203815f2e2b85b765 (diff)
Add AbstractInterface and AbstractModule
Diffstat (limited to 'AbstractModule.scala')
-rw-r--r--AbstractModule.scala20
1 files changed, 11 insertions, 9 deletions
diff --git a/AbstractModule.scala b/AbstractModule.scala
index e179c684..e7d7a5e0 100644
--- a/AbstractModule.scala
+++ b/AbstractModule.scala
@@ -4,10 +4,6 @@ import chisel3._
import chisel3.stage.ChiselStage
import chisel3.MetaConnect._
-class AbstractModule[T <: Data](params: T) {
- val ioNode = IO(params)
-}
-
object TypeArithmetic {
implicit val f1: UInt => UInt => UInt = (a: UInt) => (b: UInt) => Mux(a > b, a, b)
implicit val f2: SomeTypeContainer => Unit => SomeTypeContainer = (a: SomeTypeContainer) => (b: Unit) => a
@@ -15,20 +11,26 @@ object TypeArithmetic {
case class SomeTypeContainer(w: Int) extends UInt(w.W)
-class AbstractModuleContainer extends Module {
- val mod1 = new AbstractModule[UInt](Input(UInt(4.W)))
- val mod2 = new AbstractModule[UInt](Output(UInt(8.W)))
- val mod3 = new AbstractModule[SomeTypeContainer](Output(SomeTypeContainer(16)))
+class AbstractModuleContainer extends AbstractModule({
+ val mod1 = new AbstractInterface[UInt](Input(UInt(4.W)))
+ val mod2 = new AbstractInterface[UInt](Output(UInt(8.W)))
+ val mod3 = new AbstractInterface[SomeTypeContainer](Output(SomeTypeContainer(16)))
import TypeArithmetic._
val typeA = mod1.ioNode.makeConnection(mod2.ioNode)
val typeB = mod2.ioNode.makeConnection(mod3.ioNode)
+ // println(s"\ttypeA: ${typeA}\n\ttypeB: ${typeB}")
// need to create versions of mods1-3 with these new type params
// similar to log aggregation writer monad? but more like type aggregation
+ mod1
+})
+
+class LowerableModule extends Module {
+ val innerModule = Module(new AbstractModuleContainer)
}
object main {
def main(args: Array[String]): Unit = {
- println(chisel3.stage.ChiselStage.emitChirrtl(new AbstractModuleContainer))
+ println(chisel3.stage.ChiselStage.emitChirrtl(new LowerableModule))
}
}