AbstractModule updates to get it to output firrtlabstract-module

2 files changed, 29 insertions, 7 deletions

diff --git a/AbstractModuleStandalone.scala b/AbstractModuleStandalone.scala
index a896b1f7..2e43d3c9 100644
--- a/AbstractModuleStandalone.scala
+++ b/AbstractModuleStandalone.scala
@@ -1,4 +1,5 @@
 import chisel3._
+import chisel3.stage.ChiselStage
 
 object TypeArithmetic {
   implicit val f1: SomeTypeContainer => SomeTypeContainer => SomeTypeContainer = (a: SomeTypeContainer) => (b: SomeTypeContainer) => new SomeTypeContainer(a.i+b.i)
@@ -15,6 +16,7 @@ object TypeArithmetic {
 case class SomeTypeContainer(i: Int)
 
 object AbstractModuleStandalone {
+  class SomeModule extends Module
   def main(args: Array[String]): Unit = {
     val foo: Int = 1
     val bar: SomeTypeContainer = SomeTypeContainer(2)
@@ -26,10 +28,26 @@ object AbstractModuleStandalone {
     
     import MetaConnect._
     import TypeArithmetic._
-    bar makeConnection foo makeConnection bar makeConnection bar
-    bar makeConnection baz makeConnection foo
+    val barfoobarbar = bar makeConnection foo makeConnection bar makeConnection bar
+    val barbazfoo = bar makeConnection baz makeConnection foo
 
-    abaz makeConnection afoo
-    afoo makeConnection abar
+    val abazafoo = abaz makeConnection afoo
+    val afooabar = afoo makeConnection abar
+
+    val topIface = Seq(abazafoo, afooabar)
+    def topBody(iface: Seq[AbstractInterface[_]]): () => Module = {
+      val k = () => new SomeModule {
+        iface.foreach { x => x.params match {
+          case some: UInt => x.params.asInstanceOf[UInt] := 19.U
+          case _ => 
+        }}
+     } 
+     k
+    }
+
+    println(ChiselStage.emitFirrtl({
+      (new AbstractModule(Seq(abazafoo, afooabar))(topBody)).comp()
+    }))
   }
+
 }
diff --git a/core/src/main/scala/chisel3/AbstractModule.scala b/core/src/main/scala/chisel3/AbstractModule.scala
index 61cad9c2..b40fc758 100644
--- a/core/src/main/scala/chisel3/AbstractModule.scala
+++ b/core/src/main/scala/chisel3/AbstractModule.scala
@@ -17,14 +17,18 @@ class Op[A, B, C](func: A => B => C) {
   val f: A => B => C = func
 }
 
+class BaseAbstractModule
+
+case class PortName(s: String)
 /**
   A module that uses types from its metaconnects to type its IOs. 
   */
-class AbstractModule(iface: Seq[AbstractInterface[_]]) extends BaseModule {
+class AbstractModule(iface: Seq[AbstractInterface[_]])(body: Seq[AbstractInterface[_]] => () => Module) {
   // iface.foreach(x => {
-  //   // println(x, x.ioNode)
+  //   println(x)
   // })
   // println(iface)
+  val comp: () => Module = body(iface)
   def generateComponent(): Option[chisel3.internal.firrtl.Component] = ???
-  def initializeInParent(parentCompileOptions: chisel3.CompileOptions): Unit = ???
+  // def initializeInParent(parentCompileOptions: chisel3.CompileOptions): Unit = ???
 }