Wires should have source location information in firrtl (#2714) (#2716)

- Remove line defeating having wire locators
  `implicit val noSourceInfo = UnlocatableSourceInfo` from `WireDefault#apply`
- Add test to show locators

(cherry picked from commit f701a9f8151891e3bf9019cd3229cb3f2cd1833b)

Co-authored-by: Chick Markley <chick.markley@sifive.com>

2 files changed, 17 insertions, 2 deletions

diff --git a/core/src/main/scala/chisel3/Data.scala b/core/src/main/scala/chisel3/Data.scala
index d434735a..7c8ec1a9 100644
--- a/core/src/main/scala/chisel3/Data.scala
+++ b/core/src/main/scala/chisel3/Data.scala
@@ -9,7 +9,7 @@ import chisel3.experimental.{Analog, BaseModule, DataMirror, EnumType, FixedPoin
 import chisel3.internal.Builder.pushCommand
 import chisel3.internal._
 import chisel3.internal.firrtl._
-import chisel3.internal.sourceinfo.{DeprecatedSourceInfo, SourceInfo, SourceInfoTransform, UnlocatableSourceInfo}
+import chisel3.internal.sourceinfo.{SourceInfo, SourceInfoTransform, UnlocatableSourceInfo}
 
 import scala.collection.immutable.LazyList // Needed for 2.12 alias
 import scala.reflect.ClassTag
@@ -1075,7 +1075,6 @@ object WireDefault {
     implicit sourceInfo: SourceInfo,
     compileOptions:      CompileOptions
   ): T = {
-    implicit val noSourceInfo = UnlocatableSourceInfo
     val x = Wire(t)
     requireIsHardware(init, "wire initializer")
     x := init
diff --git a/src/test/scala/chiselTests/WireSpec.scala b/src/test/scala/chiselTests/WireSpec.scala
index 11a1f1a1..058a7f08 100644
--- a/src/test/scala/chiselTests/WireSpec.scala
+++ b/src/test/scala/chiselTests/WireSpec.scala
@@ -3,6 +3,7 @@
 package chiselTests
 
 import chisel3._
+import chisel3.stage.ChiselStage
 
 class WireSpec extends ChiselFlatSpec {
   "WireDefault.apply" should "work" in {
@@ -17,4 +18,19 @@ class WireSpec extends ChiselFlatSpec {
   it should "not allow init argument to affect type inference" in {
     assertDoesNotCompile("val x: UInt = WireDefault(UInt(4.W), 2.S)")
   }
+  it should "have source locator information on wires" in {
+    class Dummy extends chisel3.Module {
+      val in = IO(Input(Bool()))
+      val out = IO(Output(Bool()))
+
+      val wire = WireInit(Bool(), true.B)
+      val wire2 = Wire(Bool())
+      wire2 := in
+      out := in & wire & wire2
+    }
+
+    val chirrtl = ChiselStage.emitChirrtl(new Dummy)
+    chirrtl should include("wire wire : UInt<1> @[WireSpec.scala")
+    chirrtl should include("wire wire2 : UInt<1> @[WireSpec.scala")
+  }
 }