Move methods to library

4 files changed, 43 insertions, 49 deletions

diff --git a/AbstractModule.scala b/AbstractModule.scala
index 103d598f..3f6e117f 100644
--- a/AbstractModule.scala
+++ b/AbstractModule.scala
@@ -1,36 +1,36 @@
-package chiselTests
+// package chiselTests
 
-import chisel3._
-import chisel3.stage.ChiselStage
-import chisel3.MetaConnect._
+// import chisel3._
+// import chisel3.stage.ChiselStage
+// import chisel3.MetaConnect._
 
-object TypeArithmetic {
-  // implicit val f1: UInt => UInt => UInt = (a: UInt) => (b: UInt) => Mux(a > b, a, b)
-  implicit val f2: SomeTypeContainer => UInt => SomeTypeContainer = (a: SomeTypeContainer) => (b: UInt) => new SomeTypeContainer(b.litValue.toInt+a.w)
-}
+// object TypeArithmetic {
+//   // implicit val f1: UInt => UInt => UInt = (a: UInt) => (b: UInt) => Mux(a > b, a, b)
+//   implicit val f2: SomeTypeContainer => UInt => SomeTypeContainer = (a: SomeTypeContainer) => (b: UInt) => new SomeTypeContainer(b.litValue.toInt+a.w)
+// }
 
-case class SomeTypeContainer(w: Int) extends UInt(w.W)
+// case class SomeTypeContainer(w: Int) extends UInt(w.W)
 
-class AbstractModuleContainer extends AbstractModule({
-  val mod1 = new AbstractInterface[UInt](Input(UInt(4.W)))
-  val mod2 = new AbstractInterface[UInt](Output(UInt(8.W)))
-  val mod3 = new AbstractInterface[SomeTypeContainer](Output(SomeTypeContainer(16)))
+// class AbstractModuleContainer extends AbstractModule({
+//   val mod1 = new AbstractInterface[UInt](Input(UInt(4.W)))
+//   val mod2 = new AbstractInterface[UInt](Output(UInt(8.W)))
+//   val mod3 = new AbstractInterface[SomeTypeContainer](Output(SomeTypeContainer(16)))
 
-  import TypeArithmetic._
-  val typeA = mod3.ioNode.makeConnection(mod2.ioNode)
-  // val typeB = mod2.ioNode.makeConnection(mod3.ioNode)
-  // println(s"\ttypeA: ${typeA}\n\ttypeB: ${typeB}")
-  // need to create versions of mods1-3 with these new type params
-  // similar to log aggregation writer monad? but more like type aggregation
-  Seq(mod1, mod2, mod3)
-})
+//   // import TypeArithmetic._
+//   // val typeA = mod3.ioNode.makeConnection(mod2.ioNode)
+//   // // val typeB = mod2.ioNode.makeConnection(mod3.ioNode)
+//   // // println(s"\ttypeA: ${typeA}\n\ttypeB: ${typeB}")
+//   // // need to create versions of mods1-3 with these new type params
+//   // // similar to log aggregation writer monad? but more like type aggregation
+//   // Seq(mod1, mod2, mod3)
+// })
 
-class LowerableModule extends Module {
-  val innerModule = Module(new AbstractModuleContainer)
-}
+// class LowerableModule extends Module {
+//   val innerModule = Module(new AbstractModuleContainer)
+// }
 
-object main {
-  def main(args: Array[String]): Unit = {
-    println(chisel3.stage.ChiselStage.emitChirrtl(new LowerableModule))
-  }
-}
+// object main {
+//   def main(args: Array[String]): Unit = {
+//     println(chisel3.stage.ChiselStage.emitChirrtl(new LowerableModule))
+//   }
+// }
diff --git a/AbstractModuleStandalone.scala b/AbstractModuleStandalone.scala
index 050cd4f4..a896b1f7 100644
--- a/AbstractModuleStandalone.scala
+++ b/AbstractModuleStandalone.scala
@@ -1,16 +1,5 @@
 import chisel3._
 
-object MetaConnect {
-  implicit class Connection[A](that: A) {
-    def makeConnection[B, C](me: B)(implicit f: A => B => C): C = {
-      f(that)(me)
-    }
-  }
-  implicit def abstractInterfaceConnection[A, B, C](implicit f: A => B => C): AbstractInterface[A] => AbstractInterface[B] => AbstractInterface[C] = (a: AbstractInterface[A]) => (b: AbstractInterface[B]) => new AbstractInterface(f(a.params)(b.params))
-}
-
-case class AbstractInterface[T](params: T)
-
 object TypeArithmetic {
   implicit val f1: SomeTypeContainer => SomeTypeContainer => SomeTypeContainer = (a: SomeTypeContainer) => (b: SomeTypeContainer) => new SomeTypeContainer(a.i+b.i)
   implicit val f2: SomeTypeContainer => Int => SomeTypeContainer = (a: SomeTypeContainer) => (b: Int) => new SomeTypeContainer(b+a.i)
@@ -18,8 +7,9 @@ object TypeArithmetic {
     val litval: Int = 1
     new SomeTypeContainer(litval.toInt+a.i)
   }
-  // Dynamically create a wire
-  implicit val f4: UInt => UInt => (() => Any) = (a: UInt) => (b: UInt) => (() => Wire(a))
+  // Dynamically create an IO
+  // implicit val f4: UInt => UInt => (() => Any) = (a: UInt) => (b: UInt) => (() => Wire(a))
+  implicit val f5 = (new Op[UInt, UInt, () => UInt]((a: UInt) => (b: UInt) => (() => IO(a)))).f
 }
 
 case class SomeTypeContainer(i: Int)
diff --git a/core/src/main/scala/chisel3/AbstractModule.scala b/core/src/main/scala/chisel3/AbstractModule.scala
index 7c4be632..61cad9c2 100644
--- a/core/src/main/scala/chisel3/AbstractModule.scala
+++ b/core/src/main/scala/chisel3/AbstractModule.scala
@@ -9,19 +9,22 @@ import chisel3.internal.Builder._
 import chisel3.internal.firrtl._
 import chisel3.experimental.BaseModule
 
-class AbstractInterface[T <: Data](params: T) {
-  println(params)
-  val ioNode = IO(params)
+case class AbstractInterface[T](params: T)
+
+case class Interface(ifaceContainer: AbstractInterface[_]*)
+
+class Op[A, B, C](func: A => B => C) {
+  val f: A => B => C = func
 }
 
 /**
   A module that uses types from its metaconnects to type its IOs. 
   */
 class AbstractModule(iface: Seq[AbstractInterface[_]]) extends BaseModule {
-  iface.foreach(x => {
-    println(x, x.ioNode)
-  })
-  println(iface)
+  // iface.foreach(x => {
+  //   // println(x, x.ioNode)
+  // })
+  // println(iface)
   def generateComponent(): Option[chisel3.internal.firrtl.Component] = ???
   def initializeInParent(parentCompileOptions: chisel3.CompileOptions): Unit = ???
 }
diff --git a/core/src/main/scala/chisel3/MetaConnect.scala b/core/src/main/scala/chisel3/MetaConnect.scala
index 0f338e6c..acaef86f 100644
--- a/core/src/main/scala/chisel3/MetaConnect.scala
+++ b/core/src/main/scala/chisel3/MetaConnect.scala
@@ -6,4 +6,5 @@ object MetaConnect {
       f(that)(me)
     }
   }
+  implicit def abstractInterfaceConnection[A, B, C](implicit f: A => B => C): AbstractInterface[A] => AbstractInterface[B] => AbstractInterface[C] = (a: AbstractInterface[A]) => (b: AbstractInterface[B]) => new AbstractInterface(f(a.params)(b.params))
 }