diff options
| author | Schuyler Eldridge | 2019-10-23 13:59:48 -0400 |
|---|---|---|
| committer | GitHub | 2019-10-23 13:59:48 -0400 |
| commit | 2e891a4e2a638a00cb836736c72eb87673dffba3 (patch) | |
| tree | 760f33a6929b48ffe317bc6d453ca030f2aa9e59 | |
| parent | 66f5696e03a529ced36504e53f7b2fc24d31544c (diff) | |
| parent | 47bbe8c1f8d0c51d443cfa432801a56c29dc32bd (diff) | |
Merge pull request #1216 from freechipsproject/non-private-ChiselStage-targets
Make ChiselStage targets not private
| -rw-r--r-- | src/main/scala/chisel3/stage/ChiselStage.scala | 2 |
1 files changed, 1 insertions, 1 deletions
diff --git a/src/main/scala/chisel3/stage/ChiselStage.scala b/src/main/scala/chisel3/stage/ChiselStage.scala index aef1abb2..0a0cc47c 100644 --- a/src/main/scala/chisel3/stage/ChiselStage.scala +++ b/src/main/scala/chisel3/stage/ChiselStage.scala @@ -16,7 +16,7 @@ import java.io.{StringWriter, PrintWriter} class ChiselStage extends Stage with PreservesAll[Phase] { val shell: Shell = new Shell("chisel") with ChiselCli with FirrtlCli - private val targets = + val targets = Seq( classOf[chisel3.stage.phases.Checks], classOf[chisel3.stage.phases.Elaborate], classOf[chisel3.stage.phases.AddImplicitOutputFile], |