Fix LitBinding and MultiAssign tests.

2 files changed, 8 insertions, 4 deletions

diff --git a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
index df1296dd..1bdf66f1 100644
--- a/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
+++ b/chiselFrontend/src/main/scala/chisel3/core/Bits.scala
@@ -530,7 +530,7 @@ private[core] sealed trait UIntFactory {
     val lit = ULit(value, width)
     val result = new UInt(lit.width, Some(lit))
     // Bind result to being an Literal
-//    result.binding = LitBinding()
+    result.binding = LitBinding()
     result
   }
 
diff --git a/src/test/scala/chiselTests/MultiAssign.scala b/src/test/scala/chiselTests/MultiAssign.scala
index fc6c5edc..2399267e 100644
--- a/src/test/scala/chiselTests/MultiAssign.scala
+++ b/src/test/scala/chiselTests/MultiAssign.scala
@@ -34,8 +34,12 @@ class MultiAssignSpec extends ChiselFlatSpec {
   "The last assignment" should "be used when multiple assignments happen" in {
     assertTesterPasses{ new LastAssignTester }
   }
-  intercept[chisel3.internal.ChiselException] {
-//    "Reassignments to non-wire types" should "be disallowed" in {
-    assertTesterFails{ new ReassignmentTester }
+}
+
+class IllegalAssignSpec extends ChiselFlatSpec {
+  "Reassignments to non-wire types" should "be disallowed" in {
+    intercept[chisel3.internal.ChiselException] {
+      assertTesterFails{ new ReassignmentTester }
+    }
   }
 }