Fix AbstractModule invocation

2 files changed, 7 insertions, 2 deletions

diff --git a/AbstractModule.scala b/AbstractModule.scala
index e7d7a5e0..5da2550a 100644
--- a/AbstractModule.scala
+++ b/AbstractModule.scala
@@ -22,7 +22,7 @@ class AbstractModuleContainer extends AbstractModule({
   // println(s"\ttypeA: ${typeA}\n\ttypeB: ${typeB}")
   // need to create versions of mods1-3 with these new type params
   // similar to log aggregation writer monad? but more like type aggregation
-  mod1
+  Seq(mod1, mod2, mod3)
 })
 
 class LowerableModule extends Module {
diff --git a/core/src/main/scala/chisel3/AbstractModule.scala b/core/src/main/scala/chisel3/AbstractModule.scala
index e054e537..7c4be632 100644
--- a/core/src/main/scala/chisel3/AbstractModule.scala
+++ b/core/src/main/scala/chisel3/AbstractModule.scala
@@ -10,13 +10,18 @@ import chisel3.internal.firrtl._
 import chisel3.experimental.BaseModule
 
 class AbstractInterface[T <: Data](params: T) {
+  println(params)
   val ioNode = IO(params)
 }
 
 /**
   A module that uses types from its metaconnects to type its IOs. 
   */
-class AbstractModule(iface: AbstractInterface[_]*) extends BaseModule {
+class AbstractModule(iface: Seq[AbstractInterface[_]]) extends BaseModule {
+  iface.foreach(x => {
+    println(x, x.ioNode)
+  })
+  println(iface)
   def generateComponent(): Option[chisel3.internal.firrtl.Component] = ???
   def initializeInParent(parentCompileOptions: chisel3.CompileOptions): Unit = ???
 }