chiselX/src/test/resources/chisel3, branch scala3-support-chisel6 Chisel with SFC compatibility Move Chisel3 to SPDX license conventions (#1604) 2020-10-01T18:42:29+00:00 Chick Markley 2020-10-01T18:42:29+00:00 aa2c62248002de97b95523c08d7788e9715e1313 Change source and other relevant files to use SPDX license LICENSE file moved from src/ to ./ Changed license file to refer to this per recommendation using_spdx_license_list_short_identifiers WARNING: Tests fail with as of yet undiagnosed error ``` [error] Failed: Total 691, Failed 19, Errors 0, Passed 672, Ignored 15 [error] Failed tests: [error] chiselTests.QueueSpec [error] examples.VendingMachineGeneratorSpec [error] chiselTests.HarnessSpec [error] chiselTests.ConnectSpec [error] chiselTests.aop.SelectSpec [error] chiselTests.PopCountSpec [error] chiselTests.CloneModuleSpec [error] (Test / test) sbt.TestsFailedException: Tests unsuccessful [error] Total time: 379 s (06:19), completed Sep 30, 2020 12:38:17 AM sbt:chisel3> ``` 
Change source and other relevant files to use SPDX license
LICENSE file moved from src/ to ./
Changed license file to refer to this per recommendation
using_spdx_license_list_short_identifiers

WARNING: Tests fail with as of yet undiagnosed error
```
[error] Failed: Total 691, Failed 19, Errors 0, Passed 672, Ignored 15
[error] Failed tests:
[error] 	chiselTests.QueueSpec
[error] 	examples.VendingMachineGeneratorSpec
[error] 	chiselTests.HarnessSpec
[error] 	chiselTests.ConnectSpec
[error] 	chiselTests.aop.SelectSpec
[error] 	chiselTests.PopCountSpec
[error] 	chiselTests.CloneModuleSpec
[error] (Test / test) sbt.TestsFailedException: Tests unsuccessful
[error] Total time: 379 s (06:19), completed Sep 30, 2020 12:38:17 AM
sbt:chisel3>
```
 Avoid procedural wire assignment in test resource 2019-01-09T23:20:14+00:00 Schuyler Eldridge 2019-01-09T23:20:14+00:00 3d67395ef286fb309bfb645dea2b574e77d08044 Verilator 4.008 dropped the hammer on procedural wire assignment to align with the IEEE standard (first I've heard of this, though). The VerilogVendingMachine.v test resource will error in Verilator 4.008 with a PROCASSWIRE error if you try to compile it. This fixes that example to only assign to a register. Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com> 
Verilator 4.008 dropped the hammer on procedural wire assignment to
align with the IEEE standard (first I've heard of this, though). The
VerilogVendingMachine.v test resource will error in Verilator 4.008
with a PROCASSWIRE error if you try to compile it. This fixes that
example to only assign to a register.

Signed-off-by: Schuyler Eldridge <schuyler.eldridge@ibm.com>
Black box top-level IO fix (#655) 2017-07-28T21:45:09+00:00 Richard Lin 2017-07-28T21:45:09+00:00 004938693112b2be268b0ee8d91874ba2d993ec3 






Scope resources - move them down into chisel3 directory - fixes #549 (#610)
2017-05-11T22:07:30+00:00

Jim Lawson

2017-05-11T22:07:30+00:00

8baa2ab806be1aa85a7a1da7b348726da1bd1d19