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<title>chiselX/src/main/scala/chisel3/internal/firrtl, branch scala3-support</title>
<subtitle>Chisel with SFC compatibility</subtitle>
<link rel='alternate' type='text/html' href='https://git.0x7felf.com/chiselX/'/>
<entry>
<title>Use new lazy serialization in FIRRTL (#2741) (#2744)</title>
<updated>2022-09-20T20:06:44+00:00</updated>
<author>
<name>mergify[bot]</name>
</author>
<published>2022-09-20T20:06:44+00:00</published>
<link rel='alternate' type='text/html' href='https://git.0x7felf.com/chiselX/commit/?id=45909f02e86edff010902c0317e813a8753837b9'/>
<id>45909f02e86edff010902c0317e813a8753837b9</id>
<content type='text'>
This enables emission of modules that serialize to &gt;2 GiB of .fir text.

(cherry picked from commit 2cbc852d09bb63cd5da291e5d5d942ab971952a4)

Co-authored-by: Jack Koenig &lt;koenig@sifive.com&gt;</content>
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<pre>
This enables emission of modules that serialize to &gt;2 GiB of .fir text.

(cherry picked from commit 2cbc852d09bb63cd5da291e5d5d942ab971952a4)

Co-authored-by: Jack Koenig &lt;koenig@sifive.com&gt;</pre>
</div>
</content>
</entry>
<entry>
<title>Apply scalafmt</title>
<updated>2022-01-10T23:53:55+00:00</updated>
<author>
<name>Jack Koenig</name>
</author>
<published>2022-01-10T18:39:52+00:00</published>
<link rel='alternate' type='text/html' href='https://git.0x7felf.com/chiselX/commit/?id=3131c0daad41dea78bede4517669e376c41a325a'/>
<id>3131c0daad41dea78bede4517669e376c41a325a</id>
<content type='text'>
Command:
sbt scalafmtAll
</content>
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<pre>
Command:
sbt scalafmtAll
</pre>
</div>
</content>
</entry>
<entry>
<title>Emit .fir lazily, overcomes JVM 2 GiB String limit</title>
<updated>2021-08-24T00:13:48+00:00</updated>
<author>
<name>Jack Koenig</name>
</author>
<published>2021-08-20T19:00:08+00:00</published>
<link rel='alternate' type='text/html' href='https://git.0x7felf.com/chiselX/commit/?id=d9c30ea0fdd90f3e47cae161f4a7224a861a6bf0'/>
<id>d9c30ea0fdd90f3e47cae161f4a7224a861a6bf0</id>
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</content>
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<pre>
</pre>
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</content>
</entry>
<entry>
<title>Remove chisel3's own firrtl Emitter, use firrtl Serializer</title>
<updated>2021-08-24T00:13:42+00:00</updated>
<author>
<name>Jack Koenig</name>
</author>
<published>2021-08-20T18:30:27+00:00</published>
<link rel='alternate' type='text/html' href='https://git.0x7felf.com/chiselX/commit/?id=73bd4ee6b9b510725b692c33e075362a19512d2c'/>
<id>73bd4ee6b9b510725b692c33e075362a19512d2c</id>
<content type='text'>
This will be slightly slower as it involves converting from Chisel
modules to FIRRTL modules before turning them into Strings. This cost is
somewhat mitigated by doing that conversion lazily such that we never
materialize the entire firrtl Circuit in memory, only 1 module at a
time.
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<pre>
This will be slightly slower as it involves converting from Chisel
modules to FIRRTL modules before turning them into Strings. This cost is
somewhat mitigated by doing that conversion lazily such that we never
materialize the entire firrtl Circuit in memory, only 1 module at a
time.
</pre>
</div>
</content>
</entry>
<entry>
<title>Revert "remove DefRegInit, change DefReg API with option definition. (#1944)" (#2080)</title>
<updated>2021-08-18T01:22:16+00:00</updated>
<author>
<name>Jack Koenig</name>
</author>
<published>2021-08-18T01:22:16+00:00</published>
<link rel='alternate' type='text/html' href='https://git.0x7felf.com/chiselX/commit/?id=7c8a032e7e23902283035d93579b8dc477b32f6a'/>
<id>7c8a032e7e23902283035d93579b8dc477b32f6a</id>
<content type='text'>
This reverts commit ed894c61474c8bc73761a6c360ef9d14505d853b.</content>
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<pre>
This reverts commit ed894c61474c8bc73761a6c360ef9d14505d853b.</pre>
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</content>
</entry>
<entry>
<title>remove DefRegInit, change DefReg API with option definition. (#1944)</title>
<updated>2021-08-17T19:44:17+00:00</updated>
<author>
<name>Jiuyang Liu</name>
</author>
<published>2021-08-17T19:44:17+00:00</published>
<link rel='alternate' type='text/html' href='https://git.0x7felf.com/chiselX/commit/?id=ed894c61474c8bc73761a6c360ef9d14505d853b'/>
<id>ed894c61474c8bc73761a6c360ef9d14505d853b</id>
<content type='text'>
* remove DefRegInit, change DefReg API with option defination.

* add error message

* use Option[RegInitIR].

Co-authored-by: mergify[bot] &lt;37929162+mergify[bot]@users.noreply.github.com&gt;</content>
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<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
* remove DefRegInit, change DefReg API with option defination.

* add error message

* use Option[RegInitIR].

Co-authored-by: mergify[bot] &lt;37929162+mergify[bot]@users.noreply.github.com&gt;</pre>
</div>
</content>
</entry>
<entry>
<title>Make printf return BaseSim subclass so it can be named/annotated (#1992)</title>
<updated>2021-07-06T21:40:59+00:00</updated>
<author>
<name>Deborah Soung</name>
</author>
<published>2021-07-06T21:40:59+00:00</published>
<link rel='alternate' type='text/html' href='https://git.0x7felf.com/chiselX/commit/?id=503ae520e7f997bcbc639b79869c9a4214d402ed'/>
<id>503ae520e7f997bcbc639b79869c9a4214d402ed</id>
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<pre>
</pre>
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</content>
</entry>
<entry>
<title>create and extend annotatable BaseSim class for verification nodes (#1968)</title>
<updated>2021-06-24T21:03:28+00:00</updated>
<author>
<name>Deborah Soung</name>
</author>
<published>2021-06-24T21:03:28+00:00</published>
<link rel='alternate' type='text/html' href='https://git.0x7felf.com/chiselX/commit/?id=f8053db3d20b733e0119b77595f0cdfcdab71057'/>
<id>f8053db3d20b733e0119b77595f0cdfcdab71057</id>
<content type='text'>
* prototype annotating verif constructs

* switch to final class

* name emissions

* moving BaseSim to experimental

* adding name tests

* fixing quotation escapes

* emitting names, but everything has a default name

* only name things with provided/suggested names

* name every BaseSim node

* removing msg, unused imports

* fixing file exist calls</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
* prototype annotating verif constructs

* switch to final class

* name emissions

* moving BaseSim to experimental

* adding name tests

* fixing quotation escapes

* emitting names, but everything has a default name

* only name things with provided/suggested names

* name every BaseSim node

* removing msg, unused imports

* fixing file exist calls</pre>
</div>
</content>
</entry>
<entry>
<title>Remove Deprecated APIs (#1730)</title>
<updated>2021-02-04T00:36:12+00:00</updated>
<author>
<name>Jiuyang Liu</name>
</author>
<published>2021-02-04T00:36:12+00:00</published>
<link rel='alternate' type='text/html' href='https://git.0x7felf.com/chiselX/commit/?id=f45216effc573d33d4aa4e525cff955ab332efbd'/>
<id>f45216effc573d33d4aa4e525cff955ab332efbd</id>
<content type='text'>
</content>
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<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
</pre>
</div>
</content>
</entry>
<entry>
<title>Move Chisel3 to SPDX license conventions (#1604)</title>
<updated>2020-10-01T18:42:29+00:00</updated>
<author>
<name>Chick Markley</name>
</author>
<published>2020-10-01T18:42:29+00:00</published>
<link rel='alternate' type='text/html' href='https://git.0x7felf.com/chiselX/commit/?id=aa2c62248002de97b95523c08d7788e9715e1313'/>
<id>aa2c62248002de97b95523c08d7788e9715e1313</id>
<content type='text'>
Change source and other relevant files to use SPDX license
LICENSE file moved from src/ to ./
Changed license file to refer to this per recommendation
using_spdx_license_list_short_identifiers

WARNING: Tests fail with as of yet undiagnosed error
```
[error] Failed: Total 691, Failed 19, Errors 0, Passed 672, Ignored 15
[error] Failed tests:
[error] 	chiselTests.QueueSpec
[error] 	examples.VendingMachineGeneratorSpec
[error] 	chiselTests.HarnessSpec
[error] 	chiselTests.ConnectSpec
[error] 	chiselTests.aop.SelectSpec
[error] 	chiselTests.PopCountSpec
[error] 	chiselTests.CloneModuleSpec
[error] (Test / test) sbt.TestsFailedException: Tests unsuccessful
[error] Total time: 379 s (06:19), completed Sep 30, 2020 12:38:17 AM
sbt:chisel3&gt;
```</content>
<content type='xhtml'>
<div xmlns='http://www.w3.org/1999/xhtml'>
<pre>
Change source and other relevant files to use SPDX license
LICENSE file moved from src/ to ./
Changed license file to refer to this per recommendation
using_spdx_license_list_short_identifiers

WARNING: Tests fail with as of yet undiagnosed error
```
[error] Failed: Total 691, Failed 19, Errors 0, Passed 672, Ignored 15
[error] Failed tests:
[error] 	chiselTests.QueueSpec
[error] 	examples.VendingMachineGeneratorSpec
[error] 	chiselTests.HarnessSpec
[error] 	chiselTests.ConnectSpec
[error] 	chiselTests.aop.SelectSpec
[error] 	chiselTests.PopCountSpec
[error] 	chiselTests.CloneModuleSpec
[error] (Test / test) sbt.TestsFailedException: Tests unsuccessful
[error] Total time: 379 s (06:19), completed Sep 30, 2020 12:38:17 AM
sbt:chisel3&gt;
```</pre>
</div>
</content>
</entry>
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