chiselX/src/main/scala/Chisel, branch chisel6-scala3-0.1 Chisel with SFC compatibility Move chisel/... to chisel/core/..., make chisel/compatibility package/folder, move more things into utils 2016-06-08T23:22:27+00:00 ducky 2016-06-01T19:17:25+00:00 66301b9042530a5265c18c97a0dab9022a0efc50 






Rename packages to lowercase chisel, add compatibility layer
2016-06-08T23:22:27+00:00

ducky

2016-05-21T01:09:57+00:00

f36524e388b060b1bb535ae21cb1bcbbea220be9












Remove unsafe implicit conversions from BitPat
2016-06-01T02:05:31+00:00

ducky

2016-05-27T04:43:11+00:00

0b6f6b67f9b511468936ca30218343283071a69d












Move BitPat out of core/frontend, add implicit conversion
2016-06-01T02:05:25+00:00

Ducky

2016-05-23T21:09:26+00:00

2e2e3da0c07cd1dc873c064510f68123cae69059












Fix type constraint on PriorityMux
2016-05-26T08:01:55+00:00

Andrew Waterman

2016-05-26T08:01:55+00:00

3b10267257de7662abbbc235d9bfd8a8b89f69f5












Merge pull request #186 from ucb-bar/sloc_impl
2016-05-20T23:34:03+00:00

Richard Lin

2016-05-20T23:34:03+00:00

d742d70a05b5fa997517ea7b5eb2d15b23e7a431

Source locators




Source locators






Implementation of source locators
2016-05-20T23:02:49+00:00

ducky

2016-05-05T20:22:04+00:00

e92f2f69477a6ce86fc148a1a95db5797f2e3051












Update BackendCompilationUtilities.verilogToCpp to specify top-module
2016-05-20T20:38:18+00:00

jackkoenig

2016-05-20T20:38:18+00:00

d7697eb14a0195cc3726bf45fdf38c631b6f6507

This prevents Verilator from erroring when it cannot determine the top-module.
It also changes the PRINTF_COND guard to correctly use the top-level reset
instead of just the top of the Chisel-generated code.





This prevents Verilator from erroring when it cannot determine the top-module.
It also changes the PRINTF_COND guard to correctly use the top-level reset
instead of just the top of the Chisel-generated code.







remove Tester.scala because chiselMain is now implemented in the chisel-testers repo
2016-05-13T06:48:58+00:00

Danny

2016-05-13T06:48:58+00:00

a82a7034d7dce28e77e899239c9f18a7edc1c4af












RegNext and RegInit should match Reg(next=) and Reg(init=)
2016-05-11T19:58:21+00:00

Andrew Waterman

2016-05-11T19:58:21+00:00

acb04d052c9244f59ab382da569cd71b54a40256